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| ds312 march 21, 2005 www.xilinx.com 1 ? 2005 xilinx, inc. all rights reserved. xilinx, the xilinx logo, and other designated brands included herein are trademarks of xilinx, inc. all other trademarks are the property of their respective owners. module 1: introduction and ordering information ds312-1 (v1.1) march 21, 2005 6pages ? introduction features architectural overview package marking ordering information module 2: functional description ds312-2 (v1.1) march 21, 2005 96 pages input/output blocks (iobs) -overview - selectio? signal standards configurable logic block (clb) block ram dedicated multipliers digital clock manager (dcm) clock network configuration powering spartan-3e fpgas module 3: dc and switching characteristics ds312-3 (v1.0) march 1, 2005 18 pages dc electrical characteristics - absolute maximum ratings - supply voltage specifications - recommended operating conditions - dc characteristics switching characteristics - dcm timing - configuration and jtag timing module 4: pinout descriptions ds312-4 (v1.1) march 21, 2005 72 pages pin descriptions package overview pinout tables footprint diagrams important note: the spartan ? -3e fpga data sheet is created and published in separate modules. this complete version is provided for easy downloading and searching of the complete document. page, figure, and table numbers begin at 1 for each module, and each module has its own revision history at the end. use the pdf "bookmarks" for easy navigation in this volume. 0 spartan-3e fpga family: complete data sheet ds312 march 21, 2005 00 r
ds312-1 (v1.1) march 21, 2005 www.xilinx.com 1 advance product specification ? 2005 xilinx, inc. all rights reserved. xilinx, the xilinx logo, and other designated brands included herein are trademarks of xilinx, inc. all other trademarks are the property of their respective owners. introduction the spartan?-3e family of field-programmable gate arrays (fpgas) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applica- tions. the five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in ta b l e 1 . the spartan-3e family builds on the success of the earlier spartan-3 family by increasing the amount of logic per i/o, significantly reducing the cost per logic cell. new features improve system performance and reduce the cost of config- uration. these spartan-3e enhancements, combined with advanced 90 nm process technology, deliver more function- ality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. because of their exceptionally low cost, spartan-3e fpgas are ideally suited to a wide range of consumer electronics applications, including broadband access, home network- ing, display/projection, and digital television equipment. the spartan-3e family is a superior alternative to mask pro- grammed asics. fpgas avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional asics. also, fpga programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with asics. features very low cost, high-performance logic solution for high-volume, consumer-oriented applications proven advanced 90-nanometer process technology multi-voltage, multi-standard selectio? interface pins - up to 376 i/o pins or 156 differential signal pairs - lvcmos, lvttl, hstl, and sstl single-ended signal standards - true lvds, rsds, mini-lvds differential i/o - 3.3v, 2.5v, 1.8v, 1.5v, and 1.2v signaling - enhanced double data rate (ddr) support abundant, flexible logic resources - densities up to 33,192 logic cells, including optional shift register or distributed ram support - efficient wide multiplexers, wide logic - fast look-ahead carry logic - enhanced 18 x 18 multipliers with optional pipeline - ieee 1149.1/1532 jtag programming/debug port hierarchical selectram? memory architecture - up to 648 kbits of fast block ram - up to 231 kbits of efficient distributed ram up to eight digital clock managers (dcms) - clock skew elimination (delay locked loop) - frequency synthesis, multiplication, division - high-resolution phase shifting - wide frequency range (5 mhz to over 300 mhz) eight global clocks and eight clocks for each half of device, plus abundant low-skew routing configuration interface to industry-standard proms - low-cost, space-saving spi serial flash prom - x8 or x8/x16 parallel nor flash prom - low-cost xilinx platform flash with jtag complete xilinx ise?, webpack? development system support microblaze?, picoblaze ? embedded processor cores fully compliant 32-/64-bit 33/66 mhz pci support low-cost qfp and bga packaging options - common footprints support easy density migration - pb-free packaging options 06 spartan-3e fpga family: introduction and ordering information ds312-1 (v1.1) march 21, 2005 00 advance product specification r table 1: summary of spartan-3e fpga attributes device system gates equivalent logic cells clb array (one clb = four slices) distributed ram bits ( 1 ) block ram bits ( 1 ) dedicated multipliers dcms maximum user i/o maximum differential i/o pairs rows columns total clbs total slices XC3S100E 100k 2,160 22 16 240 960 15k 72k 4 2 108 40 xc3s250e 250k 5,508 34 26 612 2,448 38k 216k 12 4 172 68 xc3s500e 500k 10,476 46 34 1,164 4,656 73k 360k 20 4 232 92 xc3s1200e 1200k 19,512 60 46 2,168 8,672 136k 504k 28 8 304 124 xc3s1600e 1600k 33,192 76 58 3,688 14,752 231k 648k 36 8 376 156 notes: 1. by convention, one kb is equivalent to 1,024 bits. introduction and ordering information 2 www.xilinx.com ds312-1 (v1.1) march 21, 2005 advance product specification r architectural overview the spartan-3e family architecture consists of five funda- mental programmable functional elements: configurable logic blocks (clbs) contain flexible look-up tables (luts) that implement logic plus storage elements used as flip-flops or latches. clbs perform a wide variety of logical functions as well as store data. input/output blocks (iobs) control the flow of data between the i/o pins and the internal logic of the device. each iob supports bidirectional data flow plus 3-state operation. supports a variety of signal standards, including four high-performance differential standards. double data-rate (ddr) registers are included. block ram provides data storage in the form of 18-kbit dual-port blocks. multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. digital clock manager (dcm) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. these elements are organized as shown in figure 1 . a ring of iobs surrounds a regular array of clbs. each device has two columns of block ram except for the XC3S100E, which has one column. each ram column consists of several 18-kbit ram blocks. each block ram is associated with a dedicated multiplier. the dcms are positioned in the center with two at the top and two at the bottom of the device. the XC3S100E has only one dcm at the top and bottom, while the xc3s1200e and xc3s1600e add two dcms in the middle of the left and right sides. the spartan-3e family features a rich network of traces that interconnect all five functional elements, transmitting sig- nals among them. each functional element has an associ- ated switch matrix that permits multiple connections to the routing. figure 1: spartan-3e family architecture notes: 1. the xc3s1200e and xc3s1600e have two additional dcms on both the left and right sides as indicated by the dashed lines. the XC3S100E has only one dcm at the top and one at the bottom. introduction and ordering information ds312-1 (v1.1) march 21, 2005 www.xilinx.com 3 advance product specification r configuration spartan-3e fpgas are programmed by loading configura- tion data into robust, reprogrammable, static cmos config- uration latches (ccls) that collectively control all functional elements and routing resources. the fpga?s configuration data is stored externally in a prom or some other non-vol- atile medium, either on or off the board. after applying power, the configuration data is written to the fpga using any of seven different modes: master serial from a xilinx platform flash prom serial peripheral interface (spi) from an industry-standard spi serial flash byte peripheral interface (bpi) up or down from an industry-standard x8 or x8/x16 parallel nor flash slave serial, typically downloaded from a processor slave parallel, typically downloaded from a processor boundary scan (jtag), typically downloaded from a processor or system tester. i/o capabilities the spartan-3e fpga selectio interface supports many popular single-ended and differential standards. ta b l e 2 shows the number of user i/os as well as the number of dif- ferential i/o pairs available for each device/package combi- nation. spartan-3e fpgas support the following single-ended standards: 3.3v, low-voltage ttl, lvttl low-voltage cmos (lvcmos) at 3.3v, 2.5v, 1.8v, 1.5v, or 1.2v 3.3v pci at 33 mhz and 66 mhz hstl i and iii at 1.8v, typically for memory applications sstl i at 1.8v and 2.5v, typically for memory applications spartan-3e fpgas support the following differential stan- dards: lvds bus lvds mini-lvds rsds table 2: available user i/os and differential (diff) i/o pairs device vq100 vqg100 cp132 cpg132 tq144 tqg144 pq208 pqg208 ft256 ftg256 fg320 fgg320 fg400 fgg400 fg484 fgg484 user diff user diff user diff user diff user diff user diff user diff user diff XC3S100E 66 30 - - 108 40 - - - - - - - - - - xc3s250e 66 30 92 41 108 40 158 65 172 68 - - - - - - xc3s500e - - 92 41 - - 158 65 190 77 232 92 - - - - xc3s1200e - - - - - - - - 190 77 250 99 304 124 - - xc3s1600e - - - - - - - - - - 250 99 304 124 376 156 notes: 1. all spartan-3e devices in the same package are pin-compatible. introduction and ordering information 4 www.xilinx.com ds312-1 (v1.1) march 21, 2005 advance product specification r package marking figure 2 provides a top marking example for spartan-3e fpgas in the quad-flat packages. figure 3 shows the top marking for spartan-3e fpgas in bga packages except the 132-ball chip-scale package (cp132 and cpg132). the markings for the bga packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball a1 indicator. figure 4 shows the top marking for spartan-3e fpgas in the cp132 and cpg132 packages. use the seven digits of the lot code to access additional information for a specific device using the xilinx web-based genealogy viewer . figure 2: spartan-3e qfp example package marking lot code date code mask revision code process technology xc3s250e tm pq208agq0525 d1234567a 4c spartan device type package speed grade temperature range fabrication code pin p1 r r ds312-1_06_032105 figure 3: spartan-3e bga example package marking lot code date code xc3s250e tm 4c spartan device type bga ball a1 package speed grade temperature range r r ds312-1_02_032105 ft256agq0525 d1234567a mask revision code process code fabrication code figure 4: spartan-3e cp132 and cpg132 example package marking date code temperature range speed grade 3s250e c5agq 4c device type ball a1 lot code package c5 = cp132 c6 = cpg132 mask revision code fabrication code ds312-1_05_032105 f1234567-0525 philippines process code introduction and ordering information ds312-1 (v1.1) march 21, 2005 www.xilinx.com 5 advance product specification r ordering information spartan-3e fpgas are available in both standard and pb-free packaging options for all device/package combinations. the pb-free packages include a ?g? character in the ordering code. standard packaging pb-free packaging xc3s250e -4 ft 256 c device type speed grade temperature range: c = commercial (t j = 0 o c to 85 o c) i = industrial (t j = -40 o c to 100 o c) package type number of pins example: ds312_03_011405 xc3s250e -4 ft 256 c device type speed grade temperature range: c = commercial (t j = 0 o c to 85 o c) i = industrial (t j = -40 o c to 100 o c) package type number of pins pb-free g example: ds312_04_011405 device speed grade package type / number of pins temperature range (t j ) XC3S100E ?4 standard performance vq(g)100 100-pin very thin quad flat pack (vqfp) c commercial (0c to 85c) xc3s250e ?5 high performance cp(g)132 132-ball chip-scale package (csp) i industrial (?40c to 100c) xc3s500e tq(g)144 144-pin thin quad flat pack (tqfp) xc3s1200e pq(g)208 208-pin plastic quad flat pack (pqfp) xc3s1600e ft(g)256 256-ball fine-pitch thin ball grid array (ftbga) fg(g)320 320-ball fine-pitc h ball grid array (fbga) fg(g)400 400-ball fine-pitch ball grid array (fbga) fg(g)484 484-ball fine-pitc h ball grid array (fbga) notes: 1. the ?5 speed grade is exclusively available in the commercial temperature range. introduction and ordering information 6 www.xilinx.com ds312-1 (v1.1) march 21, 2005 advance product specification r revision history the following table shows the revision history for this document. the spartan-3e family data sheet ds312-1, spartan-3e fpga family: introduction and ordering information (module 1) ds312-2, spartan-3e fpga family: functional description (module 2) ds312-3, spartan-3e fpga family: dc and switching characteristics (module 3) ds312-4, spartan-3e fpga family: pinout descriptions (module 4) date version revision 03/01/05 1.0 initial xilinx release. 03/21/05 1.1 added xc3s250e in cp132 package to ta b l e 2 . corrected number of differential i/o pairs for cp132 package. added package markings for qfp packages ( figure 2 ) and cp132/cpg132 packages ( figure 4 ). ds312-2 (v1.1) march 21, 2005 www.xilinx.com 1 advance product specification ? 2005 xilinx, inc. all rights reserved. xilinx, the xilinx logo, and other designated brands included herein are trademarks of xilinx, inc. all other trademarks are the property of their respective owners. introduction as described in architectural overview , the spartan?-3e fpga architecture consists of five fundamental functional elements: input/output blocks (iobs) configurable logic block (clb) and slice resources block ram dedicated multipliers digital clock managers (dcms) the following sections provide detailed information on each of these functions. in addition, this section also describes the following functions: clocking infrastructure interconnect configuration powering spartan-3e fpgas input/output blocks (iobs) iob overview the input/output block (iob) provides a programmable, unidirectional or bidirectional interface between a package pin and the fpga?s internal logic. the iob is similar to that of the spartan-3 family with the following differences: input-only blocks are added programmable input delays are added to all blocks ddr flip-flops can be shared between adjacent iobs the unidirectional input-only block has a subset of the full iob capabilities. thus there are no connections or logic for an output path. the following paragraphs assume that any reference to output functionality does not apply to the input-only blocks. the number of input-only blocks varies with device size, but is never more than 25% of the total iob count. figure 1, page 2 is a simplified diagram of the iob?s internal structure. there are three main signal paths within the iob: the output path, input path, and 3-state path. each path has its own pair of storage elements that can act as either regis- ters or latches. for more information, see storage element functions . the three main signal paths are as follows: t he input path carries data from the pad, which is bonded to a package pin, through an optional programmable delay element directly to the i line. after the delay element, there are alternate routes through a pair of storage elements to the iq1 and iq2 lines. the iob outputs i, iq1, and iq2 lead to the fpga?s internal logic. the delay element can be set to ensure a hold time of zero (see input delay functions ). t he output path, starting with the o1 and o2 lines, carries data from the fpga?s internal logic through a multiplexer and then a three-state driver to the iob pad. in addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. t he 3-state path determines when the output driver is high impedance. the t1 and t2 lines carry data from the fpga?s internal logic through a multiplexer to the output driver. in addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. all signal paths entering the iob, including those associated with the storage elements, have an inverter option. any inverter placed on these paths is automatically absorbed into the iob. 096 spartan-3e fpga family: functional description ds312-2 (v1.1) march 21, 2005 00 advance product specification r functional description 2 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r figure 1: simplified iob diagram tff1 three-state path t t1 tce t2 tff2 q sr ddr mux rev q sr rev off1 output path o1 oce o2 off2 q sr ddr mux keeper latch v cco v ref pin i/o pin from adjacent iob ds312-2_19_030105 i/o pin program- mable output driver esd pull-up pull- down esd rev q sr rev otclk1 otclk2 iff1 input path iddrin1 i oddrout2 ice iff2 q sr programmable delay lvcmos, lvttl, pci single-ended standards using v ref differential standards rev d ce ck d ce ck d ce ck d ce ck d ce ck d ce ck q sr rev iddrin2 oddrin2 iclk1 iclk2 sr rev iq1 iq2 oddrin1 oddrout1 notes: 1. all iob signals communicating with the fpga?s internal logic have the option of inverting polarity inside the iob. 2. signals shown with dashed lines connect to the adjacent iob in a differential pair only, not to the fpga fabric. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 3 advance product specification r input delay functions each iob has a programmable delay block that can delay the input signal from 0 to nominally 4000 ps. in figure 2 , the signal is first delayed by either 0 or 2000 ps (nominal) and is then applied to an 8 tap delay line. this delay line has a nominal value of 250 ps per tap. all 8 taps are available via a multiplexer for use as an asynchronous input directly into the fpga fabric. in this way, the delay is programmable from 0 to 4000 ps in 250 ps steps. four of the 8 taps are also available via a multiplexer to the d inputs of the syn- chronous storage elements. the delay inserted in the path to the storage element can be varied from 0 to 4000 ps in 500 ps steps. the first, coarse delay element is common to both asynchronous and synchronous paths, and must be either used or not used for both paths. the delay values are set up in the silicon once at configura- tion time?they are non-modifiable in device operation. the primary use for the input delay element is as an ade- quate delay to ensure that there is no hold time requirement when using the input flip-flop(s) with a global clock. the necessary value for this function is chosen by the xilinx soft- ware tools and depends on device size. if the design is using a dcm in the clock path, then the delay element can be safely set to zero in the user's design, and there is still no hold time requirement. both asynchronous and synchronous values can be modi- fied by the user, which is useful where extra delay is required on clock or data inputs, for example, in interfaces to various types of ram. see module 3 of the spartan-3e data sheet for exact values for the delay elements. figure 2: input delay elements pad asynchronous input (i) synchronous input (iq2) synchronous input (iq1) dq dq ds312-2_18_022205 functional description 4 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r storage element functions there are three pairs of storage elements in each iob, one pair for each of the three paths. it is possible to configure each of these storage elements as an edge-triggered d-type flip-flop (fd) or a level-sensitive latch (ld). the storage-element pair on either the output path or the three-state path can be used together with a special multi- plexer to produce double-data-rate (ddr) transmission. this is accomplished by taking data synchronized to the clock signal?s rising edge and converting it to bits syn- chronized on both the rising and the falling edge. the com- bination of two registers and a multiplexer is referred to as a double-data-rate d-type flip-flop (oddr2). ta b l e 1 describes the signal paths associated with the stor- age element. as shown in figure 1 , the upper registers in both the output and three-state paths share a common clock. the otclk1 clock signal drives the ck clock inputs of the upper registers on the output and three-state paths. similarly, otclk2 drives the ck inputs for the lower registers on the output and three-state paths. the upper and lower registers on the input path have independent clock lines: iclk1 and iclk2. the oce enable line controls the ce inputs of the upper and lower registers on the output path. similarly, tce con- trols the ce inputs for the register pair on the three-state path and ice does the same for the register pair on the input path. the set/reset (sr) line entering the iob controls all six registers, as is the reverse (rev) line. in addition to the signal polarity controls described in iob overview , each storage element additionally supports the controls described in ta b l e 2 . table 1: storage element signal description storage element signal description function d data input data at this input is stored on the active edge of ck and enabled by ce. for latch operation when the input is enabled, data passes directly to the output q. q data output the data on this output reflects the state of the storage element. for operation as a latch in transparent mode, q mirrors the data at d. ck clock input data is loaded into the storage element on this input?s active edge with ce asserted. ce clock enable input when asserted, this input enables ck. if not connected, ce defaults to the asserted state. sr set/reset input this input forces the storage element into the state specified by the srhigh/srlow attributes. the sync/async attribute setting determines if the sr input is synchronized to the clock or not. if both sr and rev are active at the same time, the storage element gets a value of 0. rev reverse input this input is used together with sr. it forces the storage element into the state opposite from what sr does. the sync/async attribute setting determines whether the rev input is synchronized to the clock or not. if both sr and rev are active at the same time, the storage element gets a value of 0. table 2: storage element options option switch function specificity ff/latch chooses between an edge-triggered flip-flop or a level-sensitive latch independent for each storage element sync/async determines whether the sr set/reset control is synchronous or asynchronous independent for each storage element functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 5 advance product specification r double-data-rate transmission double-data-rate (ddr) transmission describes the tech- nique of synchronizing signals to both the rising and falling edges of the clock signal. spartan-3e devices use register pairs in all three iob paths to perform ddr operations. the pair of storage elements on the iob?s output path (off1 and off2), used as registers, combine with a spe- cial multiplexer to form a ddr d-type flip-flop (oddr2). this primitive permits ddr transmission where output data bits are synchronized to both the rising and falling edges of a clock. ddr operation requires two clock signals (usually 50% duty cycle), one the inverted form of the other. these signals trigger the two registers in alternating fashion, as shown in figure 3 . the digital clock manager (dcm) gen- erates the two clock signals by mirroring an incoming signal, and then shifting it 180 degrees. this approach ensures minimal skew between the two signals. alternatively, the inverter inside the iob can be used to invert the clock sig- nal, thus only using one clock line and both rising and falling edges of that clock line as the two clocks for the ddr flip-flops. the storage-element pair on the three-state path (tff1 and tff2) also can be combined with a local multiplexer to form a ddr primitive. this permits synchronizing the output enable to both the rising and falling edges of a clock. this ddr operation is realized in the same way as for the output path. the storage-element pair on the input path (iff1 and iff2) allows an i/o to receive a ddr signal. an incoming ddr clock signal triggers one register, and the inverted clock sig- nal triggers the other register. the registers take turns cap- turing bits of the incoming ddr data signal. the primitive to allow this functionality is called iddr2. aside from high bandwidth data transfers, ddr outputs also can be used to reproduce, or mirror , a clock signal on the output. this approach is used to transmit clock and data sig- nals together (source synchronously). a similar approach is used to reproduce a clock signal at multiple outputs. the advantage for both approaches is that skew across the out- puts is minimal. srhigh/srlow determines whether sr acts as a set, which forces the storage element to a logic "1" (srhigh) or a reset, which forces a logic "0" (srlow) independent for each storage element, except when using oddr2. in the latter case, the selection for the upper element will apply to both elements. init1/init0 when global set/reset (gsr) is asserted or after configuration this option specifies the initial state of the storage element, either set (init1) or reset (init0). by default, choosing srlow also selects init0; choosing srhigh also selects init1. independent for each storage element, except when using oddr2, which uses two iobs. in the oddr2 case, selecting init0 for one iobs applies to both elements within the iob, although init1 could be selected for the elements in the other iob. table 2: storage element options option switch function specificity figure 3: two methods for clocking the ddr register ds312-2_20_021105 d1 clk1 ddr mux dcm q1 fddr d2 clk2 q2 180? 0? q d1 clk1 ddr mux dcm q1 fddr d2 clk2 q2 0? q functional description 6 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r register cascade feature in the spartan-3e family, one of the iobs in a differential pair can cascade either its input or output storage elements with those in the other iob of the differential pair. this is intended to make ddr operation at high speed much sim- pler to implement. the new ddr connections that are avail- able are shown in figure 1 (dashed lines), and are only available for routing between iobs and are not accessible to the fpga fabric. note that this feature is only available when using differential i/o. iddr2 as a ddr input pair, the master iob registers incoming data on the rising edge of iclk1 (= d1) and the rising edge of iclk2 (= d2), which is typically the same as the falling edge of iclk1. this data is then transferred into the fpga fabric. at some point, both signals must be brought into the same clock domain, typically iclk1. this can be difficult at high frequencies because the available time is only one half of a clock cycle assuming a 50% duty cycle. see figure 4 for a graphical illustration of this function. in the spartan-3e device, the signal d2 can be cascaded into the storage element of the adjacent slave iob. there it is re-registered to iclk1, and only then fed to the fpga fabric where it is now already in the same time domain as d1. here, the fpga fabric uses only the clock iclk1 to pro- cess the received data. see figure 5 for a graphical illustra- tion of this function. oddr2 as a ddr output pair, the master iob registers data coming from the fpga fabric on the rising edge of oclk1 (= d1) and the rising edge of oclk2 (= d2), which is typically the same as the falling edge of oclk1. these two bits of data are multiplexed by the ddr mux and forwarded to the out- put pin. at some point in the fpga fabric, the signal d2 must be brought into the clock domain oclk2 from the domain oclk1. this can be difficult at high frequencies, because the time available is only one half a clock cycle. see figure 6 for a graphical illustration of this function. in the spartan-3e device, the signal d2 can be cascaded via the storage element of the adjacent slave iob. here, it is registered by oclk1 and then forwarded to the master iob where it is re-registered to oclk2, selected as usual by the ddr multiplexer, and then forwarded to the output pin. this way the data for transmission can be processed using just the clock oclk1 in the fpga fabric. see figure 7 for a graphical illustration of this function. figure 4: input ddr (without cascade feature) iclk2 to fabric pad d1 d2 d pad iclk1 d1 d2 d d+2 d+4 d+6 d+8 d+8 d+7 d+6 d+5 d+4 d+3 d+2 d+1 d-1 d+1 d+3 d+5 d+7 d q iclk1 iclk2 ds312-2_21_021105 d q figure 5: input ddr using spartan-3e cascade feature d q iclk1 to fabric pad d1 d2 pad iclk2 d q iclk1 iclk2 d q iq2 iddrin2 d1 d2 d-1 d+1 d+3 d+5 d+7 d d+2 d+4 d+6 d+8 d d+8 d+7 d+6 d+5 d+4 d+3 d+2 d+1 ds312-2_22_030105 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 7 advance product specification r selectio signal standards the spartan-3e i/os feature inputs and outputs that sup- port a wide range of i/o signaling standards ( ta b l e 3 and ta b l e 4 ). the majority of the i/os also can be used to form differential pairs to support any of the differential signaling standards ( ta bl e 4 ). to define the i/o signaling standard in a design, set the iostandard attribute to the appropriate setting. xilinx provides a variety of different methods for applying the iostandard for maximum flexibility. for a full description of different methods of applying attributes to control iostandard, refer to ?entry strategies for xilinx con- straints? in the xilinx software manuals and help. spartan-3e fpgas provide additional input flexibility by allowing i/o standards to be mixed in different banks. spe- cial care must be taken to ensure the input voltages do not exceed v cco (see module 3 for the specifications). for a particular v cco voltage, ta b l e 3 and ta b l e 4 list all of the iostandards that can be combined and if the iostan- dard is supported as an input only or can be used for both inputs and outputs. figure 6: output ddr (without cascade feature) d q oclk1 from fabric pad d2 d1 d+4 d+3 d+2 d+1 d pad oclk1 d1 d2 oclk2 d q oclk2 ds312-2_23_030105 d+1 d+3 d+5 d+7 d d+2 d+4 d+6 d+8 d+9 d+8 d+10 d+5 d+6 d+7 figure 7: output ddr using spartan-3e cascade feature d q oclk1 from fabric pad d2 d1 d+4 d+3 d+2 d+1 d pad oclk1 oclk2 d q oclk2 ds312-2_36_030105 d q oddrout1 oddrin2 d1 d2 d+1 d+3 d+5 d+7 d+9 d d+2 d+4 d+6 d+8 d+5 d+6 d+7 d+8 functional description 8 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r table 3: single-ended iostandard bank compatibility single-ended iostandard v cco supply/compatibility input requirements 1.2 v 1.5 v 1.8 v 2.5 v 3.0 v 3.3 v v ref for inputs board termination voltage (v tt ) lvttl - - - - - input/ output n/r n/r lvcm os 33 - - - - - input/ output n/r n/r lvcm os 25 - - - input/ output input input n/r n/r lvcm os 18 - - input/ output input input input n/r n/r lvcm os 15 - input/ output input input input input n/r n/r lvcm os 12 input/ output input input input input input n/r (1) n/r pci33_3 - - - - input/ output input n/r n/r pci66_3 - - - - input/ output input n/r n/r pcix input/ output input n/r n/r hstl_i_18 - - input/ output input input input 0.9 0.9 hstl_iii_18 - - input/ output input input input 1.1 1.8 sstl18_i - - input/ output input input input 0.9 0.9 sstl2_i - - - input/ output input input 1.25 1.25 notes: 1. n/r - not required for input operation. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 9 advance product specification r hstl and sstl inputs use the reference voltage (v ref ) to bias the input-switching threshold. once a configuration data file is loaded into the fpga that calls for the i/os of a given bank to use hstl/sstl, a few specifically reserved i/o pins on the same bank automatically convert to v ref inputs. for banks that do not contain hstl or sstl, v ref pins remain available for user i/os or input pins. differential standards employ a pair of signals, one the opposite polarity of the other. the noise canceling proper- ties (for example, common-mode rejection) of these stan- dards permit exceptionally high data transfer rates. this subsection introduces the differential signaling capabilities of spartan-3e devices. each device-package combination designates specific i/o pairs specially optimized to support differential standards. differential pairs can be shown in the pin and area con- straints editor (pace) with the ?show differential pairs? option. a unique l-number , part of the pin name, identifies the line-pairs associated with each bank (see module 4 ). for each pair, the letters p and n designate the true and inverted lines, respectively. for example, the pin names io_l43p_3 and io_l43n_3 indicate the true and inverted lines comprising the line pair l43 on bank 3. v cco provides current to the outputs and additionally pow- ers the on-chip differential termination. v cco must be 2.5v when using the on-chip differential termination. the v ref lines are not required for differential operation. to further understand how to combine multiple iostan- dards within a bank, refer to iobs organized into banks , page 10 . on-chip differential termination spartan-3e devices provide an on-chip 100 ? differential termination across the input differential receiver terminals (see module 3 for the specific range). the on-chip input dif- ferential termination in spartan-3e devices eliminates the external 100 ? termination resistor commonly found in dif- ferential receiver circuits. use differential termination for lvds, mini-lvds, and blvds as applications permit. on-chip differential termination is available in banks with v cco = 2.5v and is not supported on dedicated input pins. set the diff_term attribute to true to enable differential termination on a differential i/o pin pair. the diff_term attribute uses the following syntax in the ucf file: inst diff_term = ? functional description 10 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r pull-down resistors are commonly applied to unused i/os, inputs, and three-state outputs, but can be used on any i/o. the pull-up resistor connects an i/o to v cco through a resistor. the resistance value depends on the v cco voltage (see module 3 for the specifications). the pull-down resistor similarly connects an i/o to ground with a resistor. the pul- lup and pulldown attributes and library primitives turn on these optional resistors. by default, pulldown resistors terminate all unused i/os. unused i/os can alternatively be set to pullup or float. to change the unused i/o pad setting, set the bitstream generator (bitgen) option unusedpin to pullup, pull- down, or float. the unusedpin option is accessed through the properties for generate programming file in ise. during configuration a low logic level on hswap activates the pull-up resistors for all i/os not used directly in the selected configuration mode. keeper circuit each i/o has an optional keeper circuit (see figure 9 ) that keeps bus lines from floating when not being actively driven. the keeper circuit retains the last logic level on a line after all drivers have been turned off. apply the keeper attribute or use the keeper library primitive to use the keeper circuitry. pull-up and pull-down resistors override the keeper settings. slew rate control and drive strength each iob has a slew-rate control that sets the output switching edge-rate for lvcmos and lvttl outputs. the slew attribute controls the slew rate and can either be set to slow (default) or fast. each lvcmos and lvttl output additionally supports up to six different drive current strengths as shown in ta b l e 5 . to adjust the drive strength for each output set the drive attribute to the desired drive strength: 2, 4, 6, 8, 12, and 16. high output current drive strength and fast output slew rates generally result in fastest i/o performance. however, these same settings generally also result in transmission line effects on the printed circuit board (pcb) for all but the shortest board traces. each iob has independent slew rate and drive strength controls. use the slowest slew rate and lowest output drive current that meets the performance requirements for the end application. likewise, due to lead inductance, a given package supports a limited number of simultaneous switching outputs (ssos) when using fast, high-drive outputs. only use fast, high-drive outputs when required by the application. iobs organized into banks the spartan-3e architecture organizes iobs into four i/o banks as shown in figure 10 . each bank maintains sepa- rate v cco and v ref supplies. the separate supplies allow each bank to independently set v cco . similarly, the v ref supplies may be set for each bank. refer to ta b l e 3 and ta b l e 4 for v cco and v ref requirements. when working with spartan-3e devices, most of the differ- ential i/o standards are compatible and can be combined within any given bank. each bank can support any two of the following differential standards: lvds_25 outputs, mini_lvds_25 outputs, and rsds_25 outputs. as an example, lvds_25 outputs, rsds_25 outputs, and any other differential inputs while using on-chip differential ter- mination are a valid combination. a combination not allowed is a single bank with lvds_25 outputs, rsds_25 outputs, and mini_lvds_25 outputs. figure 9: keeper circuit weak pull-up weak pull-down input path output path keeper ds312-2_25_022805 ta b l e 5 : programmable output drive current signal standard output drive current (ma) 2 4 6 8 12 16 lvttl lv c m o s 3 3 lv c m o s 2 5 - lv c m o s 1 8 - - lv c m o s 1 5 - - - lv c m o s 1 2 - - - - - functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 11 advance product specification r i/o banking rules when assigning i/os to banks, these v cco rules must be followed: 1. all v cco pins on the fpga must be connected even if a bank is unused. 2. all v cco lines associated within a bank must be set to the same voltage level. 3. the v cco levels used by all standards assigned to the i/os of any given bank must agree. the xilinx development software checks for this. ta b l e 3 and ta b l e 4 describe how different standards use the v cco supply. 4. if a bank does not have any v cco requirements, connect v cco to an available voltage, such as 2.5v or 3.3v. some configuration modes might place additional v cco requirements. refer to configuration , page 56 for more information. if any of the standards assigned to the inputs of the bank use v ref , then the following additional rules must be observed: 1. all v ref pins must be connected within a bank. 2. all v ref lines associated with the bank must be set to the same voltage level. 3. the v ref levels used by all standards assigned to the inputs of the bank must agree. the xilinx development software checks for this. ta b l e 3 describes how different standards use the v ref supply. if v ref is not required to bias the input switching thresholds, all associated v ref pins within the bank can be used as user i/os or input pins. package footprint compatibility sometimes, applications outgrow the logic capacity of a specific spartan-3e fpga. fortunately, the spartan-3e family is designed so that multiple part types are available in pin-compatible package footprints, as described in module 4 . in some cases, there are subtle differences between devices available in the same footprint. these differences are outlined for each package, such as pins that are uncon- nected on one device but connected on another in the same package or pins that are dedicated inputs on one package but full i/o on another. when designing the printed circuit board (pcb), plan for potential future upgrades and pack- age migration. the spartan-3e family is not pin-compatible with any previ- ous xilinx fpga family. dedicated inputs dedicated inputs are iobs used only as inputs. pin names designate a dedicated input if the name starts with ip , for example, ip or ip_lxxx_x. dedicated inputs retain the full functionality of the iob for input functions with a single exception for differential inputs (ip_lxxx_x). for the differ- ential dedicated inputs, the on-chip differential termination is not available. to replace the on-chip differential termina- tion, choose a differential pair that supports outputs (io_lxxx_x) or use an external 100 ? termination resistor on the board. esd protection clamp diodes protect all device pads against damage from electro-static discharge (esd) as well as excessive voltage transients. each i/o has two clamp diodes: one diode extends p-to-n from the pad to v cco and a second diode extends n-to-p from the pad to gnd. during operation, these diodes are normally biased in the off state. these clamp diodes are always connected to the pad, regardless of the signal standard selected. the presence of diodes lim- its the ability of spartan-3e i/os to tolerate high signal volt- ages. the v in absolute maximum rating in table 1 of module 3 specifies the voltage range that i/os can tolerate. supply voltages for the iobs the iobs are powered by three supplies: 1. the v cco supplies, one for each of the fpga?s i/o banks, power the output drivers. the voltage on the v cco pins determines the voltage swing of the output signal. 2. v ccint is the main power supply for the fpga?s internal logic. 3. v ccaux is an auxiliary source of power, primarily to optimize the performance of various fpga functions such as i/o switching. the i/os during power-on , configuration, and user mode all i/os have esd clamp diodes to their respective v cco supply and from gnd, as shown in figure 1 . the v ccint (1.2v), v ccaux (2.5v), and v cco supplies can be applied in any order. before the fpga can start its configuration pro- cess, v ccint , v cco bank 2, and v ccaux must have reached their respective minimum recommended operating figure 10: spartan-3e i/o banks (top view) ds312-2_26_021205 bank 0 bank 2 bank 3 bank 1 functional description 12 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r levels (see table 2 of module 3 ). at this time, all i/o drivers are in a high-impedance state. v cco bank 2, v ccint , and v ccaux serve as inputs to the internal power-on reset cir- cuit (por). a low level applied to the hswap input enables pull-up resistors on user i/os from power-on throughout configura- tion. a high level on hswap disables the pull-up resistors, allowing the i/os to float. hswap contains a weak pull-up and defaults to high if left floating. as soon as power is applied, the fpga begins initializing its configuration mem- ory. at the same time, the fpga internally asserts the glo- bal set-reset (gsr), which asynchronously resets all iob storage elements to a default low state. upon the completion of initialization and the beginning of configuration, init_b goes high, sampling the m0, m1, and m2 inputs to determine the configuration mode. at this point in time, the configuration data is loaded into the fpga. the i/o drivers remain in a high-impedance state (with or with- out pull-up resistors, as determined by the hswap input) throughout configuration. at the end of configuration, the gsr net is released, placing the iob registers in a low state by default, unless the loaded design reverses the polarity of their respective sr inputs. the global three state (gts) net is released during start-up, marking the end of configuration and the begin- ning of design operation in the user mode. after the gts net is released, all user i/os go active while all unused i/os are weakly pulled down (pulldown). the designer can control how the unused i/os are terminated after gts is released by setting the bitstream generator (bitgen) option unusedpin to pullup, pulldown, or float. one clock cycle later (default), the global write enable (gwe) net is released allowing the ram and registers to change states. once in user mode, any pull-up resistors enabled by hswap revert to the user settings and hswap is available as a general-purpose i/o. for more information on pullup and pulldown, see pull-up and pull-down resistors . jtag boundary-scan capability all spartan-3e iobs support boundary-scan testing com- patible with ieee 1149.1/1532 standards. see jtag mode , page 86 for more information on programming via jtag. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 13 advance product specification r configurable logic block (clb) and slice resources clb overview the configurable logic blocks (clbs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. each clb contains four slices, and each slice contains two look-up tables (luts) to imple- ment logic and two dedicated storage elements that can be used as flip-flops or latches. the luts can be used as a 16x1 memory (ram16) or as a 16-bit shift register (srl16), and additional multiplexers and carry logic simplify wide logic and arithmetic functions. most general-purpose logic in a design is automatically mapped to the slice resources in the clbs. each clb is identical, and the spartan-3e family clb structure is identical to that for the spartan-3 family. clb array the clbs are arranged in a regular array of rows and col- umns as shown in figure 11 . each density varies by the number of rows and columns of clbs (see ta b l e 6 ). slices each clb comprises four interconnected slices, as shown in figure 13 . these slices are grouped in pairs. each pair is organized as a column with an independent carry chain. the left pair supports both logic and memory functions and its slices are called slicem. the right pair supports logic only and its slices are called slicel. therefore half the luts support both logic and memory (including both ram16 and srl16 shift registers) while half support logic only, and the two types alternate throughout the array col- umns. the slicel reduces the size of the clb and lowers the cost of the device, and can also provide a performance advantage over the slicem. figure 11: clb locations ds312-2_31_021205 spartan-3e fpga x0y1 x1y1 x0y0 x1y0 iobs clb slice x2y1 x3y1 x2y0 x3y0 x0y3 x1y3 x0y2 x1y2 x2y3 x3y3 x2y2 x3y2 table 6: spartan-3e clb resources device clb rows clb columns clb total (1) slices luts / flip-flops equivalent logic cells ram16 / srl16 distributed ram bits XC3S100E 22 16 240 960 1920 2160 960 15360 xc3s250e 34 26 612 2448 4896 5508 2448 39168 xc3s500e 46 34 1164 4656 9312 10476 4656 74496 xc3s1200e 60 46 2168 8672 17344 19512 8672 138752 xc3s1600e 76 58 3688 14752 29504 33192 14752 236032 notes: 1. the number of clbs is less than the multiple of the rows and columns because the block ram/multiplier blocks and the dcms are embedded in the array (see module 1 , figure 1). functional description 14 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r . figure 12: simplified diagram of the left-hand slicem wf[4:1] ds312-2_32_021205 notes: 1. options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. the index i can be 6, 7, or 8, depending on the slice. the upper slicel has an f8mux, and the upper slicem has an f7mux. the lower slicel and slicem both have an f6mux. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 15 advance product specification r slice location designations the xilinx development software designates the location of a slice according to its x and y coordinates, starting in the bottom left corner, as shown in figure 11 . the letter ?x? fol- lowed by a number identifies columns of slices, increment- ing from the left side of the die to the right. the letter ?y? followed by a number identifies the position of each slice in a pair as well as indicating the clb row, incrementing from the bottom of the die. figure 13 shows the clb located in the lower left-hand corner of the die. the slicem always has an even ?x? number, and the slicel always has an odd ?x? number. slice overview a slice includes two lut function generators and two stor- age elements, along with additional logic, as shown in figure 14 . both slicem and slicel have the following elements in common to provide logic, arithmetic, and rom functions: two 4-input lut function generators, f and g two storage elements two wide-function multiplexers, f5mux and fimux carry and arithmetic logic figure 13: arrangement of slices within the clb ds099-2_05_082104 interconnect to neighbors left-hand slicem (logic or distributed ram or shift register) right-hand slicel (logic only) cin slice x0y1 slice x0y0 switch matrix cout clb cout shiftout shiftin cin slice x1y1 slice x1y0 figure 14: resources in a slice fimux f5mux register carry carry register arithmetic logic slicem slicel srl16 ram16 lut4 (g) srl16 ram16 lut4 (f) fimux f5mux register carry carry register arithmetic logic lut4 (g) lut4 (f) ds312-2_13_020905 functional description 16 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the slicem pair supports two additional functions: two 16x1 distributed ram blocks, ram16 two 16-bit shift registers, srl16 each of these elements is described in more detail in the fol- lowing sections. logic cells the combination of a lut and a storage element is known as a "logic cell". the additional features in a slice, such as the wide multiplexers, carry logic, and arithmetic gates, add to the capacity of a slice, implementing logic that would oth- erwise require additional luts. benchmarks have shown that the overall slice is equivalent to 2.25 simple logic cells. this calculation provides the equivalent logic cell count shown in ta bl e 6 . slice details figure 16 is a detailed diagram of the slicem. it represents a superset of the elements and connections to be found in all slices. the dashed and gray lines (blue when viewed in color) indicate the resources found only in the slicem and not in the slicel. each slice has two halves, which are differentiated as top and bottom to keep them distinct from the upper and lower slices in a clb. the control inputs for the clock (clk), clock enable (ce), slice write enable (slicewe1), and reset/set (rs) are shared in common between the two halves. the luts located in the top and bottom portions of the slice are referred to as "g" and "f", respectively, or the "g-lut" and the "f-lut". the storage elements in the top and bot- tom portions of the slice are called ffy and ffx, respec- tively. each slice has two multiplexers with f5mux in the bottom portion of the slice and fimux in the top portion. depending on the slice, the fimux takes on the name f6mux, f7mux, or f8mux, according to its position in the multi- plexer chain. the lower slicel and slicem both have an f6mux. the upper slicem has an f7mux, and the upper slicel has an f8mux. the carry chain enters the bottom of the slice as cin and exits at the top as cout. five multiplexers control the chain: cyinit, cy0f, and cymuxf in the bottom portion and cy0g and cymuxg in the top portion. the dedicated arith- metic logic includes the exclusive-or gates xorf and xorg (bottom and top portions of the slice, respectively) as well as the and gates fand and gand (bottom and top portions, respectively). see ta b l e 7 for a description of all the slice input and output signals. table 7: slice inputs and outputs name location direction description f[4:1] slicel/m bottom input f-lut and fand inputs g[4:1] slicel/m top input g-lut and gand inputs or write address (slicem) bx slicel/m bottom input bypass to or output (slicem) or storage element, or control input to f5mux, input to carry logic, or data input to ram (slicem) by slicel/m top input bypass to or output (slicem) or storage element, or control input to fimux, input to carry logic, or data input to ram (slicem) bxout slicem bottom output bx bypass output byout slicem top output by bypass output altdig slicem top input alternate data input to ram dig slicem top output altdig or shiftin bypass output slicewe1 slicem common input ram write enable f5 slicel/m bottom output output from f5mux; direct feedback to fimux fxina slicel/m top input input to fimux; direct feedback from f5mux or another fimux fxinb slicel/m top input input to fimux; direct feedback from f5mux or another fimux fi slicel/m top output output from fimux; direct feedback to another fimux ce slicel/m common input ffx/y clock enable sr slicel/m common input ffx/y set or reset or ram write enable (slicem) functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 17 advance product specification r main logic paths central to the operation of each slice are two nearly identi- cal data paths at the top and bottom of the slice. the description that follows uses names associated with the bot- tom path. (the top path names appear in parentheses.) the basic path originates at an interconnect switch matrix out- side the clb. see interconnect for more information on the switch matrix and the routing connections. four lines, f1 through f4 (or g1 through g4 on the upper path), enter the slice and connect directly to the lut. once inside the slice, the lower 4-bit path passes through a lut "f" (or "g") that performs logic operations. the lut data output, "d", offers five possible paths: 1. exit the slice via line "x" (or "y") and return to interconnect. 2. inside the slice, "x" (or "y") serves as an input to the dxmux (or dymux) which feeds the data input, "d", of the ffy (or ffx) storage element. the "q" output of the storage element drives the line xq (or yq) which exits the slice. 3. control the cymuxf (or cymuxg) multiplexer on the carry chain. 4. with the carry chain, serve as an input to the xorf (or xorg) exclusive-or gate that performs arithmetic operations, producing a result on "x" (or "y"). 5. drive the multiplexer f5mux to implement logic functions wider than four bits. the "d" outputs of both the f-lut and g-lut serve as data inputs to this multiplexer. in addition to the main logic paths described above, there are two bypass paths that enter the slice as bx and by. once inside the fpga, bx in the bottom half of the slice (or by in the top half) can take any of several possible branches: 1. bypass both the lut and the storage element, and then exit the slice as bxout (or byout) and return to interconnect. 2. bypass the lut, and then pass through a storage element via the d input before exiting as xq (or yq). 3. control the wide function multiplexer f5mux (or fimux). 4. via multiplexers, serve as an input to the carry chain. 5. drive the di input of the lut. 6. by can control the rev inputs of both the ffy and ffx storage elements. see storage element functions . 7. finally, the dig_mux multiplexer can switch by onto the dig line, which exits the slice. the control inputs clk, ce, sr, bx and by have program- mable polarity. the lut inputs do not need programmable polarity because their function can be inverted inside the lut. the sections that follow provide more detail on individual functions of the slice. look-up tables the look-up table or lut is a ram-based function gener- ator and is the main resource for implementing logic func- tions. furthermore, the luts in each slicem pair can be configured as distributed ram or a 16-bit shift register, as described later. each of the two luts (f and g) in a slice have four logic inputs (a1-a4) and a single output (d). any four-variable boolean logic operation can be implemented in one lut. functions with more inputs can be implemented by cascad- clk slicel/m common input ffx/y clock or ram clock (slicem) shiftin slicem top input data input to g-lut ram shiftout slicem bottom output shift data output from f-lut ram cin slicel/m bottom input carry chain input cout slicel/m top output carry chain output x slicel/m bottom output combinatorial output y slicel/m top output combinatorial output xb slicel/m bottom output combinatorial output from carry or f-lut srl16 (slicem) yb slicel/m top output combinatorial output from carry or g-lut srl16 (slicem) xq slicel/m bottom output ffx output yq slicel/m top output ffy output table 7: slice inputs and outputs (continued) name location direction description functional description 18 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r ing luts or by using the wide function multiplexers that are described later. the output of the lut can connect to the wide multiplexer logic, the carry and arithmetic logic, or directly to a clb out- put or to the clb storage element. see figure 15 . wide multiplexers wide-function multiplexers effectively combine luts in order to permit more complex logic operations. each slice has two of these multiplexers with f5mux in the bottom por- tion of the slice and fimux in the top portion. the f5mux multiplexes the two luts in a slice. the fimux multiplexes two clb inputs which connect directly to the f5mux and fimux results from the same slice or from other slices. see figure 16 . depending on the slice, fimux takes on the name f6mux, f7mux, or f8mux. the designation indicates the number of inputs possible without restriction on the function. for example, an f7mux can generate any function of seven inputs. figure 17 shows the names of the multiplexers in each position in the spartan-3e clb. the figure also includes the direct connections within the clb, along with the f7mux connection to the clb below. each mux can create logic functions of more inputs than indicated by its name. the f5mux, for example, can gener- ate any function of five inputs, with four inputs duplicated to two luts and the fifth input controlling the mux. because each lut can implement independent 2:1 muxes, the f5mux can combine them to create a 4:1 mux, which is a six-input function. if the two luts have completely indepen- dent sets of inputs, some functions of all nine inputs can be implemented. ta b l e 8 shows the connections for each mul- tiplexer and the number of inputs possible for different types of functions. figure 15: lut resources in a slice a[4:1] f[4:1] 4 ds312-2_33_022205 f-lut g[4:1] d a[4:1] yq y g-lut ffy ffx d xq x figure 16: dedicated multiplexers in spartan-3e clb fimux fx (local feedback to fxin) y (general interconnect) yq 0 1 0 1 fxina fxinb f[4:1] g[4:1] dq f5mux by bx f5 (local feedback to fxin) x (general interconnect) xq dq lut lut x312-2_34_021205 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 19 advance product specification r figure 17: muxes and dedicated feedback in spartan-3e clb ds312-2_38_021305 f5 f8 f5 f6 f5 f7 f5 f6 f5 fx f5 fx f5 x fxina fxinb fxina fxinb fxina fxinb fxina fxinb f5 fx table 8: mux capabilities mux usage input source total number of inputs per function for any function for mux for limited functions f5mux f5mux luts 5 6 (4:1 mux) 9 fimux f6mux f5mux 6 11 (8:1 mux) 19 f7mux f6mux 7 20 (16:1 mux) 39 f8mux f7mux 8 37 (32:1 mux) 79 functional description 20 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the wide multiplexers can be used by the automatic tools or instantiated in a design using a component such as the f5mux. the symbol, signals, and function are described below. the description is similar for the f6mux, f7mux, and f8mux. each has versions with a general output, local output, or both. for more details on using the multiplexers, see x app466 : "using dedicated multiplexers in spartan-3 fpgas". carry and arithmetic logic the carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math operations. the carry logic is automatically used for most arithmetic functions in a design. the gates and multi- plexers of the carry and arithmetic logic can also be used for general-purpose logic, including simple wide boolean func- tions. the carry chain enters the slice as cin and exits as cout, controlled by several multiplexers. the carry chain connects directly from one clb to the clb above. the carry chain can be initialized at any point from the bx (or by) inputs. the dedicated arithmetic logic includes the exclusive-or gates xorf and xorg (upper and lower portions of the slice, respectively) as well as the and gates gand and fand (upper and lower portions, respectively). these gates work in conjunction with the luts to implement efficient arithmetic functions, including counters and multipliers, typ- ically at two bits per slice. see figure 19 and ta b l e 1 1 . figure 18: f5mux with local and general outputs table 9: f5mux inputs and outputs signal function i0 input selected when s is low i1 input selected when s is high s select input lo local output that connects to the f5 or fx clb pins, which use local feedback to the fxin inputs to the fimux for cascading o general output that connects to the general-purpose combinatorial or registered outputs of the clb o i0 i1 0 1 s lo ds312-2_35_021205 table 10: f5mux function inputs outputs si0i1 o lo 01 x1 1 00 x0 0 1 x1 1 1 1 x0 0 0 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 21 advance product specification r figure 19: carry logic table 11: carry logic functions function description cyinit initializes carry chain for a slice. fixed selection of: ? cin carry input from the slice below ? bx input cy0f carry generation for bottom half of slice. fixed selection of: ? f1 or f2 inputs to the lut (both equal 1 when a carry is to be generated) ? fand gate for multiplication ? bx input for carry initialization ? fixed "1" or "0" input for use as a simple boolean function cy0g carry generation for top half of slice. fixed selection of: ? g1 or g2 inputs to the lut (both equal 1 when a carry is to be generated) ? gand gate for multiplication ? by input for carry initialization ? fixed "1" or "0" input for use as a simple boolean function cymuxf carry generation or propagation mux for bottom half of slice. dynamic selection via cyself of: ? cyinit carry propagation (cyself = 1) ? cy0f carry generation (cyself = 0) cy0f cyself 1 xorf d a[4:1] f[4:1] 4 cymuxf cyinit xb xq x 0 1 cin ds312-2_14_021305 fand f1 f2 bx f-lut ffx g[4:1] cy0g cyselg 1 xorg d a[4:1] cymuxg yb cout yq y 0 1 gand g1 g2 by g-lut ffy functional description 22 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the basic usage of the carry logic is to generate a half-sum in the lut via an xor function, which generates or propa- gates a carry out cout via the carry mux cymuxf (or cymuxg), and then complete the sum with the dedicated xorf (or xorg) gate and the carry input cin. this struc- ture allows two bits of an arithmetic function in each slice. the cymuxf (or cymuxg) can be instantiated using the muxcy element, and the xorf (or xorg) can be instan- tiated using the xorcy element. the fand (or gand) gate is used for partial product multi- plication and can be instantiated using the mult_and component. partial products are generated by two-input and gates and then added. the carry logic is efficient for the adder, but one of the inputs must be outside the lut as shown in figure 20 . the fand (or gand) gate is used to duplicate one of the partial products, while the lut gener- ates both partial products and the xor function, as shown in figure 21 . cymuxg carry generation or propagation mux for top half of slice. dynamic selection via cyself of: ? cymuxf carry propagation (cyselg = 1) ? cy0g carry generation (cyselg = 0) cyself carry generation or propagation select for bottom half of slice. fixed selection of: ? f-lut output (typically xor result) ? fixed "1" to always propagate cyselg carry generation or propagation select for top half of slice. fixed selection of: ? g-lut output (typically xor result) ? fixed "1" to always propagate xorf sum generation for bottom half of slice. inputs from: ? f-lut ? cyinit carry signal from previous stage result is sent to either the combinatorial or registered output for the top of the slice. xorg sum generation for top half of slice. inputs from: ? g-lut ? cymuxf carry signal from previous stage result is sent to either the combinatorial or registered output for the top of the slice. fand multiplier partial product for bottom half of slice. inputs: ? f-lut f1 input ? f-lut f2 input result is sent through cy0f to become the carry generate signal into cymuxf gand multiplier partial product for top half of slice. inputs: ? g-lut g1 input ? g-lut g2 input result is sent through cy0g to become the carry generate signal into cymuxg table 11: carry logic functions (continued) function description figure 20: using the muxcy and xorcy in the carry logic xorcy lut muxcy b a sum cin ds312-2_37_021305 cout figure 21: using the mult_and for multiplication in carry logic b n+1 a m b n a m+1 p m+1 cin ds312-2_39_021305 cout lut mult_and functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 23 advance product specification r the mult_and is useful for small multipliers. larger multi- pliers can be built using the dedicated 18x18 multiplier blocks (see dedicated multipliers ). storage elements the storage element, which is programmable as either a d-type flip-flop or a level-sensitive transparent latch, pro- vides a means for synchronizing data to a clock signal, among other uses. the storage elements in the top and bot- tom portions of the slice are called ffy and ffx, respec- tively. ffy has a fixed multiplexer on the d input selecting either the combinatorial output y or the bypass signal by. ffx selects between the combinatorial output x or the bypass signal bx. the functionality of a slice storage element is identical to that described earlier for the i/o storage elements. all sig- nals have programmable polarity; the default active-high function is described. the control inputs r, s, ce, and c are all shared between the two flip-flops in a slice. table 12: storage element signals signal description d input. for a flip-flop data on the d input is loaded when r and s (or clr and pre) are low and ce is high during the low-to-high clock transition. for a latch, q reflects the d input while the gate (g) input and gate enable (ge) are high and r and s (or clr and pre) are low. the data on the d input during the high-to-low gate transition is stored in the latch. the data on the q output of the latch remains unchanged as long as g or ge remains low. q output. toggles after the low-to-high clock transition for a flip-flop and immediately for a latch. c clock for edge-triggered flip-flops. g gate for level-sensitive latches. ce clock enable for flip-flops. ge gate enable for latches. s synchronous set (q = high). when the s input is high and r is low, the flip-flop is set, output high, during the low-to-high clock (c) transition. a latch output is immediately set, output high. r synchronous reset (q = low); has precedence over set. pre asynchronous preset (q = high). when the pre input is high and clr is low, the flip-flop is set, output high, during the low-to-high clock (c) transition. a latch output is immediately set, output high. clr asynchronous clear (q = low); has precedence over preset to reset q output low sr clb input for r, s, clr, or pre rev clb input for opposite of sr. must be asynchronous or synchronous to match sr. figure 22: fd flip-flop component with synchronous reset, set, and clock enable fdrse dq ce c r s ds312-2_40_021305 table 13: fd flip-flop functionality with synchronous reset, set, and clock enable inputs outputs rscedc q 1 x x x 0 01 x x 1 000 x x no change 0011 1 0010 0 functional description 24 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r initialization the clb storage elements are initialized at power-up, dur- ing configuration, by the global gsr signal, and by the indi- vidual sr or rev inputs to the clb. distributed ram the luts in the slicem can be programmed as distributed ram. this type of memory affords moderate amounts of data buffering anywhere along a data path. one slicem lut stores 16 bits (ram16). the four lut inputs f[4:1] or g[4:1] become the address lines labeled a[4:1] in the device model and a[3:0] in the design components, provid- ing a 16x1 configuration in one lut. multiple slicem luts can be combined in various ways to store larger amounts of data, including 16x4, 32x2, or 64x1 configurations in one clb. the fifth and sixth address lines required for the 32-deep and 64-deep configurations, respectively, are implemented using the bx and by inputs, which connect to the write enable logic for writing and the f5mux and f6mux for reading. writing to distributed ram is always synchronous to the slicem clock (wclk for distributed ram) and enabled by the slicem sr input which functions as the active-high write enable (we). the read operation is asynchronous, and, therefore, during a write, the output initially reflects the old data at the address being written. the distributed ram outputs can be captured using the flip-flops within the slicem element. the we write-enable control for the ram and the ce clock-enable control for the flip-flop are independent, but the wclk and clk clock inputs are shared. because the ram read operation is asynchronous, the output data always reflects the currently addressed ram location. a dual-port option combines two luts so that memory access is possible from two independent data lines. the same data is written to both 16x1 memories but they have independent read address lines and outputs. the dual-port function is implemented by cascading the g-lut address lines, which are used for both read and write, to the f-lut write address lines (wf[4:1] in figure 12 ), and by cascad- ing the g-lut data input d1 through the dif_mux in figure 12 and to the d1 input on the f-lut. one clb pro- vides a 16x1 dual-port memory as shown in figure 23 . any write operation on the d input and any read operation on the spo output can occur simultaneously with and inde- pendently from a read operation on the second read-only port, dpo. table 14: slice storage element initialization signal description sr set/reset input. forces the storage element into the state specified by the attribute srhigh or srlow. srhigh forces a logic ?1? when sr is asserted. srlow forces a logic ?0?. for each slice, set and reset can be set to be synchronous or asynchronous. rev reverse of set/reset input. a second input (by) forces the storage element into the opposite state. the reset condition is predominant over the set condition if both are active. same synchronous/asynchronous setting as for sr. gsr global set/reset. gsr defaults to active high but can be inverted by adding an inverter in front of the gsr input of the startup_spartan3e element. the initial state after configuration or gsr is defined by a separate init0 and init1 attribute. by default, setting the srlow attribute sets init0, and setting the srhigh attribute sets init1. figure 23: ram16x1d dual-port usage d a[3:0] we wclk spo dpo dpra[3:0] 16x1 lut ram (read/ write) 16x1 lut ram (read only) optional register optional register slicem ds312-2_41_021305 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 25 advance product specification r the init attribute can be used to preload the memory with data during fpga configuration. the default initial contents for ram is all zeros. if the we is held low, the element can be considered a rom. the rom function is possible even in the slicel. the global write enable signal, gwe, is asserted automati- cally at the end of device configuration to enable all writable elements. the gwe signal guarantees that the initialized distributed ram contents are not disturbed during the con- figuration process. the distributed ram is useful for smaller amounts of mem- ory. larger memory requirements can use the dedicated 18kbit ram blocks (see block ram ). for more information on distributed ram, see x app464 : "using look-up tables as distributed ram in spartan-3 fpgas". shift registers it is possible to program each slicem lut as a 16-bit shift register (see figure 25 ). used in this way, each lut can delay serial data anywhere from 1 to 16 clock cycles without using any of the dedicated flip-flops. the resulting program- mable delays can be used to balance the timing of data pipelines. the slicem luts cascade from the g-lut to the f-lut through the difmux (see figure 12 ). shiftin and shiftout lines cascade a slicem to the slicem below to form larger shift registers. the four slicem luts of a single clb can be combined to produce delays up to 64 clock cycles. it is also possible to combine shift registers across more than one clb. figure 24: dual-port ram component table 15: dual-port ram function inputs outputs we (mode) wclk d spo dpo 0 (read) x x data_a data_d 1 (read) 0 x data_a data_d 1 (read) 1 x data_a data_d 1 (write) d d data_d 1 (read) x data_a data_d notes: 1. data_a = word addressed by bits a3-a0. 2. data_d = word addressed by bits dpra3-dpra0. table 16: distributed ram signals signal description wclk the clock is used for synchronous writes. the data and the address input pins have setup times referenced to the wclk pin. active on the positive edge by default with built-in programmable polarity. we the enable pin affects the write functionality of the port. an inactive write enable prevents any writing to memory cells. an active write enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs. active high by default with built-in programmable polarity. ram16x1d we spo d wclk a0 a1 a2 a3 dpra0 dpra1 dpra2 dpra3 dpo ds312-2_42_021305 a0, a1, a2, a3 (a4, a5) the address inputs select the memory cells for read or write. the width of the port determines the required address inputs. d the data input provides the new data value to be written into the ram. o, spo, and dpo the data output o on single-port ram or the spo and dpo outputs on dual-port ram reflects the contents of the memory cells referenced by the address inputs. following an active write clock edge, the data out (o or spo) reflects the newly written data. table 16: distributed ram signals (continued) signal description functional description 26 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r each shift register provides a shift output mc15 for the last bit in each lut, in addition to providing addressable access to any bit in the shift register through the normal d output. the address inputs a[3:0] are the same as the distributed ram address lines, which come from the lut inputs f[4:1] or g[4:1]. at the end of the shift register, the clb flip-flop can be used to provide one more shift delay for the addres- sable bit. the shift register element is known as the srl16 (shift register lut 16-bit), with a ?c? added to signify a cascade ability (q15 output) and ?e? to indicate a clock enable. see figure 26 for an example of the srlc16e component. i the functionality of the shift register is shown in ta bl e 1 7 . the srl16 shifts on the rising edge of the clock input when the clock enable control is high. this shift register cannot be initialized either during configuration or during operation except by shifting data into it. the clock enable and clock inputs are shared between the two luts in a slicem. the clock enable input is automatically kept active if unused. for more information on the srl16, refer to x app465 : "using look-up tables as shift registers (srl16) in spartan-3 fpgas". figure 25: logic cell srl16 structure a[3:0] shiftin shiftout or yb di (by) d mc15 di wsg ce (sr) clk srlc16 d q shift-reg we ck a[3:0] output registered output (optional) 4 x465_03_040203 ws figure 26: srl16 shift register component with cascade and clock enable table 17: srl16 shift register function inputs outputs am clk ce d q q15 am x0 xq[am] q[15] am 1dq[am-1] q[15] notes: 1. m = 0, 1, 2, 3. srlc16e dq ce clk a0 a1 a2 a3 q15 ds312-2_43_021305 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 27 advance product specification r block ram spartan-3e devices incorporate 4 to 36 dedicated block rams, which are organized as dual-port configurable 18 kbit blocks. functionally, the block ram is identical to the spartan-3 architecture block ram. block ram synchro- nously stores large amounts of data while distributed ram, previously described, is better suited for buffering small amounts of data anywhere along signal paths. this section describes basic block ram functions. for detailed imple- mentation information, refer to xapp463 : "using block ram in spartan-3 series fpgas". each block ram is configurable by setting the content?s ini- tial values, default signal value of the output registers, port aspect ratios, and write modes. block ram can be used in single-port or dual-port modes. arrangement of ram blocks on die the block rams are located together with the multipliers on the die in one or two columns depending on the size of the device. the XC3S100E has one column of block ram. the spartan-3e devices ranging from the xc3s250e to xc3s1600e have two columns of block ram. ta bl e 1 8 shows the number of ram blocks, the data storage capac- ity, and the number of columns for each device. row(s) of clbs are located above and below each block ram col- umn. immediately adjacent to each block ram is an embedded 18x18 hardware multiplier. the upper 16 bits of the block ram's port a data input bus are shared with the upper 16 bits of the a multiplicand input bus of the multiplier. similarly, the upper 16 bits of port b's data input bus are shared with the b multiplicand input bus of the multiplier. details on the block ram?s shared connectivity with the multipliers are located in xapp463 . the internal structure of the block ram the block ram has a dual port structure. the two identical data ports called a and b permit independent access to the common block ram, which has a maximum capacity of 18,432 bits, or 16,384 bits with no parity bits (see parity bits description in ta b l e 1 9 ). each port has its own dedicated set of data, control, and clock lines for synchronous read and write operations. there are four basic data paths, as shown in figure 27 : 1. write to and read from port a 2. write to and read from port b 3. data transfer from port a to port b 4. data transfer from port b to port a number of ports a choice among primitives determines whether the block ram functions as dual- or single-port memory. a name of the form ramb16_s[w a ]_s[w b ] calls out the dual-port prim- itive, where the integers w a and w b specify the total data path width at ports a and b, respectively. thus, a ramb16_s9_s18 is a dual-port ram with a 9-bit port a and an 18-bit port b. a name of the form ramb16_s[w] identifies the single-port primitive, where the integer w specifies the total data path width of the lone port a. a ramb16_s18 is a single-port ram with an 18-bit port. port aspect ratios each port of the block ram can be configured indepen- dently to select a number of different possible widths for the data input (di) and data output (do) signals as shown in ta b l e 1 9 . table 18: number of ram blocks by device device total number of ram blocks total addressable locations (bits) number of columns XC3S100E 4 73,728 1 xc3s250e 12 221,184 2 xc3s500e 20 368,640 2 xc3s1200e 28 516,096 2 xc3s1600e 36 663,552 2 figure 27: block ram data paths ds312-2_01_020705 spartan-3e dual-port block ram read 3 read write write read write write read port a port b 2 1 4 functional description 28 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r if the data bus width of port a differs from that of port b, the block ram automatically performs a bus-matching function as described in figure 28 . when data is written to a port with a narrow bus and then read from a port with a wide bus, the latter port effectively combines ?narrow? words to form ?wide? words. similarly, when data is written into a port with a wide bus and then read from a port with a narrow bus, the latter port divides ?wide? words to form ?narrow? words. par- ity bits are not available if the data port width is configured as x4, x2, or x1. for example, if a x36 data word (32 data, 4 parity) is addressed as two x18 halfwords (16 data, 2 par- ity), the parity bits associated with each data byte are mapped within the block ram to the appropriate parity bits. the same effect happens when the x36 data word is mapped as four x9 words. table 19: port aspect ratios total data path width (w bits) di/do data bus width (w-p bits) 1 dip/dop parity bus width (p bits) addr bus width (r bits) 2 di/do [w-p-1:0] dip/dop [p-1:0] addr [r-1:0] no. of addressable locations (n) 3 block ram capacity (w*n bits) 4 1 1 0 14 [0:0] - [13:0] 16,384 16,384 2 2 0 13 [1:0] - [12:0] 8,192 16,384 4 4 0 12 [3:0] - [11:0] 4,096 16,384 9 8 1 11 [7:0] [0:0] [10:0] 2,048 18,432 18 16 2 10 [15:0] [1:0] [9:0] 1,024 18,432 36 32 4 9 [31:0] [3:0] [8:0] 512 18,432 notes: 1. the width of the total data path (w) is the sum of the di/do bus width (w-p) and any parity bits (p). 2. the width selection made for the di/do bus determines the number of address lines (r) according to the relationship expressed as: r = 14 ? [log(w?p)/log(2)]. 3. the number of address lines delimits the total number (n) of addressable locations or depth according to the following equati on: n = 2 r . 4. the product of w and n yields the total block ram capacity. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 29 advance product specification r block ram port signal definitions representations of the dual-port primitive ramb16_s[w a ]_s[w b ] and the single-port primitive ramb16_s[w] with their associated signals are shown in figure 29a and figure 29b , respectively. these signals are defined in ta bl e 2 0 . the control signals (we, en, clk, and ssr) on the block ram are active high. however, optional inverters on the control signals change the polarity of the active edge to active low. figure 28: data organization and bus-matching operation with different port widths on port a and port b byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 0 1 2 3 4 5 6 7 b y t e 3 0 0 1 0 1 2 3 0 1 6 7 0 1 2 3 4 5 6 7 byte 0 0 1 2 3 4 5 6 7 byte 3 0 1 2 3 p0 p2 p0 p1 p2 p3 p2 p3 p0 p1 p3 p1 0 1 2 3 byte 0 4 5 6 7 byte 3 0 1 2 3 c d e f 1c 1d 1e 1f 16 17 8 15 0 8 16 24 32 33 34 35 31 23 15 7 0 7 0 7 8 2 3 0 1 2 3 4 5 6 7 y t e 0 0 1 0 1 0 address 512x36 1kx18 2kx9 4kx4 8kx2 16kx1 parity data b ds312-2_02_020705 no parity (16kbits data) parity optional (16kbits data, 2kbits parity) functional description 30 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r figure 29: block ram primitives ds312-2_03_021305 wea ena ssra clka addra[r a ?:0] dia[w a ? a ?:0] dipa[p a ?:0] dopa[p a ?:0] doa[w a ? a ?:0] ramb16_w a _w b (a) dual-port (b) single-port dopb[p b ?:0] dob[w b ? b ?:0] web enb ssrb clkb addrb[r b ?:0] dib[w b ? b ?:0] dipb[p b ?:0] we en ssr clk addr[r?:0] di[w??:0] dip[p?:0] dop[p?:0] do[w??:0] ramb16_sw notes: 1. w a and w b are integers representing the total data path width (i.e., data bits plus parity bits) at ports a and b, respectively. 2. p a and p b are integers that indicate the number of data path lines serving as parity bits. 3. r a and r b are integers representing the address bus width at ports a and b, respectively. 4. the control signals clk, we, en, and ssr on both ports have the option of inverted polarity. table 20: block ram port signals signal description port a signal name port b signal name direction function address bus addra addrb input the address bus selects a memory location for read or write operations. the width (w) of the port?s associated data path determines the number of available address lines (r), as per ta b l e 1 8 . data input bus dia dib input data at the di input bus is written to the ram location specified by the address input bus (addr) during the active edge of the clk input, when the clock enable (en) and write enable (we) inputs are active. it is possible to configure a port?s di input bus width (w-p) based on ta b l e 1 8 . this selection applies to both the di and do paths of a given port. parity data input(s) dipa dipb input parity inputs represent additional bits included in the data input path. although referred to herein as ?parity? bits, the parity inputs and outputs have no special functionality for generating or checking parity and can be used as additional data bits. the number of parity bits ?p? included in the di (same as for the do bus) depends on a port?s total data path width (w). see ta bl e 1 8 . functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 31 advance product specification r block ram attribute definitions a block ram has a number of attributes that control its behavior as shown in ta bl e 2 1 . data output bus doa dob output data is written to the do output bus from the ram location specified by the address input bus, addr. see the di signal description for do port width configurations. basic data access occurs on the active edge of the clk when we is inactive and en is active. the do outputs mirror the data stored in the address addr memory location. data access with we active if the write_mode attribute is set to the value: write_first, which accesses data after the write takes place. read_first accesses data before the write occurs. a third attribute, no_change, latches the do outputs upon the assertion of we. see block ram data operations for details on the write_mode attribute. parity data output(s) dopa dopb output parity outputs represent additional bits included in the data input path. the number of parity bits ?p? included in the di bus (same as for the do bus) depends on a port?s total data path width (w). see the dip signal description for configuration details. write enable wea web input when asserted together with en, this input enables the writing of data to the ram. when we is inactive with en asserted, read operations are still possible. in this case, a latch passes data from the addressed memory location to the do outputs. clock enable ena enb input when asserted, this input enables the clk signal to perform read and write operations to the block ram. when inactive, the block ram does not perform any read or write operations. set/reset ssra ssrb input when asserted, this pin forces the do output latch to the value of the srval attribute. it is synchronized to the clk signal. clock clka clkb input this input accepts the clock signal to which read and write operations are synchronized. all associated port inputs are required to meet setup times with respect to the clock signal?s active edge. the data output bus responds after a clock-to-out delay referenced to the clock signal?s active edge. table 20: block ram port signals (continued) signal description port a signal name port b signal name direction function table 21: block ram attributes function attribute possible values initial content for data memory, loaded during configuration initxx (init_00 through init3f) each initialization string defines 32 hex values of the 16384-bit data memory of the block ram. initial content for parity memory, loaded during configuration initpxx (initp_00 through initp0f) each initialization string defines 32 hex values of the 2048-bit parity data memory of the block ram. data output latch initialization init (single-port) inita , initb (dual-port) hex value the width of the chosen port. functional description 32 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r block ram data operations writing data to and accessing data from the block ram are synchronous operations that take place independently on each of the two ports. ta b l e 2 2 describes the data opera- tions of each port as a result of the block ram control sig- nals in their default active-high edges. the waveforms for the write operation are shown in the top half of figure 30 , figure 31 , and figure 32 . when the we and en signals enable the active edge of clk, data at the di input bus is written to the block ram location addressed by the addr lines. data output latch synchronous set/reset value srval (single-port) srval_a , srval_b (dual-port) hex value the width of the chosen port. data output latch behavior during write (see block ram data operations ) write_mode write_first, read_first, no_change table 21: block ram attributes (continued) function attribute possible values table 22: block ram function table input signals output signals ram data gsr en ssr we clk addr dip di dop do parity data immediately after configuration loaded during configuration x x initp_xx init_xx global set/reset immediately after configuration 1 x x x x x x x init init no chg no chg ram disabled 0 0 x x x x x x no chg no chg no chg no chg synchronous set/reset 0110 x x x srval srval no chg no chg synchronous set/reset during write ram 0111 addr pdata data srval srval ram(addr) pdata ram(addr) data read ram, no write operation 0100 addr x x ram(pdata) ram(data) no chg no chg write ram, simultaneous read operation 0101 addr pdata data write_mode = write_first pdata data ram(addr) pdata ram(addr) data write_mode = read_first ram(data) ram(data) ram(addr) pdata ram(addr) pdata write_mode = no_change no chg no chg ram(addr) pdata ram(addr) pdata functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 33 advance product specification r there are a number of different conditions under which data can be accessed at the do outputs. basic data access always occurs when the we input is inactive. under this condition, data stored in the memory location addressed by the addr lines passes through a output latch to the do outputs. the timing for basic data access is shown in the portions of figure 30 , figure 31 , and figure 32 during which we is low. data also can be accessed on the do outputs when assert- ing the we input based on the value of the write_mode attribute as described in ta b l e 2 3 . setting the write_mode attribute to a value of write_first, data is written to the addressed memory location on an enabled active clk edge and is also passed to the do outputs. write_first timing is shown in the portion of figure 30 during which we is high. setting the write_mode attribute to a value of read_first, data already stored in the addressed loca- tion passes to the do outputs before that location is over- written with new data from the di inputs on an enabled active clk edge. read_first timing is shown in the por- tion of figure 31 during which we is high. table 23: write_mode effect on data output latches during write operations write mode effect on same port effect on opposite port (dual-port only with same address) write_first read after write data on di and dip inputs is written into specified ram location and simultaneously appears on do and dop outputs. invalidates data on do and dop outputs. read_first read before write data from specified ram location appears on do and dop outputs. data on di and dip inputs is written into specified location. data from specified ram location appears on do and dop outputs. no_change no read on write data on do and dop outputs remains unchanged. data on di and dip inputs is written into specified location. invalidates data on do and dop outputs. figure 30: waveforms of block ram data operations with write_first selected clk we di addr do en disabled read xxxx 1111 2222 xxxx aa bb cc dd 0000 mem(aa) 1111 2222 mem(dd) read write mem(bb)=1111 write mem(cc)=2222 ds312-2_05_020905 data_in internal memory do data_out = data_in di functional description 34 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r setting the write_mode attribute to a value of no_change, puts the do outputs in a latched state when asserting we. under this condition, the do outputs retain the data driven just before we is asserted. no_change timing is shown in the portion of figure 32 during which we is high. figure 31: waveforms of block ram data operations with read_first selected clk we di addr do en disabled read xxxx 1111 2222 xxxx aa bb cc dd 0000 mem(aa) old mem(bb) old mem(cc) mem(dd) read write mem(bb)=1111 write mem(cc)=2222 ds312-2_06_020905 data_in internal memory do prior stored data di figure 32: waveforms of block ram data operations with no_change selected clk we di addr do en disabled read xxxx 1111 2222 xxxx aa bb cc dd 0000 mem(aa) mem(dd) read write mem(bb)=1111 write mem(cc)=2222 ds312-2_07_020905 data_in internal memory do no change during write di functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 35 advance product specification r dedicated multipliers the spartan-3e devices provide 4 to 36 dedicated multiplier blocks per device. the multipliers are located together with the block ram in one or two columns depending on device density. see arrangement of ram blocks on die for details on the location of these blocks and their connectivity. the multiplier blocks primarily perform two?s complement numerical multiplication but can also perform some less obvious applications such as simple data storage and barrel shifting. logic slices also implement efficient small multipli- ers and thereby supplement the dedicated multipliers. the spartan-3e dedicated multiplier blocks have additional fea- tures beyond those provided in spartan-3 fpgas. each multiplier performs the principle operation p = a b, where ?a? and ?b? are 18-bit words in two?s complement form, and ?p? is the full-precision 36-bit product, also in two?s complement form. the 18-bit inputs represent values rang- ing from -131,072 10 to +131,071 10 with a resulting product ranging from -17,179,738,112 10 to +17,179,869,184 10 . implement multipliers with inputs less than 18 bits by sign-extending the inputs (i.e., replicating the most-signifi- cant bit). wider multiplication operations are performed by combining the dedicated multipliers and slice-based logic in any viable combination or by time-sharing a single multi- plier. perform unsigned multiplication by restricting the inputs to the positive range. tie the most-significant bit low and represent the unsigned value in the remaining 17 lesser-significant bits. as shown in figure 33 , each multiplier block has optional registers on each of the multiplier inputs and the output. the registers are named areg, breg, and preg and can be used in any combination. the clock input is common to all the registers within a block, but each register has an inde- pendent clock enable and synchronous reset controls mak- ing them ideal for storing data samples and coefficients. when used for pipelining, the registers boost the multiplier clock rate, beneficial for higher performance applications. figure 33 illustrates the principle features of the multiplier block. use the mult18x18sio primitive shown in figure 34 to instantiate a multiplier within a design. although high-level logic synthesis software usually automatically infers a multi- plier, adding the pipeline registers usually requires the mult18x18sio primitive. connect the appropriate signals to the mult18x18sio multiplier ports and set the individual areg, breg, and preg attributes to ?1? to insert the asso- ciated register, or to 0 to remove it and make the signal path combinatorial. figure 33: principle ports and functions of dedicated multiplier blocks x ce cea areg (optional) breg (optional) rsta a[17:0] p[35:0] dq rst ce cep preg (optional) rstp dq rst ce ceb rstb b[17:0] clk dq rst ds312-2_27_021205 functional description 36 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the mult18x18sio primitive has two additional ports called bcin and bcout to cascade or share the multi- plier?s ?b? input among several multiplier bocks. the 18-bit bcin "cascade" input port offers an alternate input source from the more typical ?b? input. the b_input attribute spec- ifies whether the specific implementation uses the bcin or ?b? input path. setting b_input to direct chooses the ?b? input. setting b_input to cascade selects the alternate bcin input. the breg register then optionally holds the selected input value, if required. bcout is an 18-bit output port that always reflects the value that is applied to the multiplier?s second input, which is either the ?b? input, the cascaded value from the bcin input, or the output of the breg if it is inserted. figure 35 illustrates the four possible configurations using different settings for the b_input attribute and the breg attribute. figure 34: mult18x18sio primitive mult18x18sio a[17:0] p[35:0] bcout[17:0] b[17:0] cea ceb cep clk rsta rstb rstp bcin[17:0] ds312-2_28_021205 figure 35: four configurations of the b input x ce ceb rstb bcin[17:0] bcin[17:0] clk dq rst bcout[17:0] breg = 1 b_input = cascade breg = 0 b_input = cascade x ce ceb rstb b[17:0] breg breg clk dq rst bcout[17:0] breg = 1 b_input = direct x bcout[17:0] b[17:0] breg = 0 b_input = direct x bcout[17:0] ds312-2_29_021505 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 37 advance product specification r the bcin and bcout ports have associated dedicated routing that connects adjacent multipliers within the same column. via the cascade connection, the bcout port of one multiplier block drives the bcin port of the multiplier block directly above it. there is no connection to the bcin port of the bottom-most multiplier block in a column or a connection from the bcout port of the top-most block in a column. as an example, figure 36 shows the multiplier cas- cade capability within the XC3S100E fpga, which has a single column of multiplier, four blocks tall. for clarity, the figure omits the register control inputs. when using the breg register, the cascade connection forms a shift register structure typically used in dsp algo- rithms such as direct-form fir filters. when the breg reg- ister is omitted, the cascade structure essentially feeds the same input value to more than one multiplier. this parallel connection serves to create wide-input multipliers, imple- ment transpose fir filters, and is used in any application that requires that several multipliers have the same input value. figure 36: multiplier cascade connection bcout bcin b_input = cascade a p b a b a b a b ds312-2_30_021505 bcout bcin b_input = cascade p bcout bcin b_input = cascade p bcout bcin b_input = direct p functional description 38 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r ta b l e 2 4 defines each port of the mult18x18sio primitive. table 24: mult18x18sio embedded multiplier primitives description signal name direction function a[17:0] input the primary 18-bit two?s complement value for multiplication. the block multiplies by this value asynchronously if the optional areg and preg registers are omitted. when areg and/or preg are used, the value provided on this port is qualified by the rising edge of clk, subject to the appropriate register controls. b[17:0] input the second 18-bit two?s complement value for multiplication if the b_input attribute is set to direct. the block multiplies by this value asynchronously if the optional breg and preg registers are omitted. when breg and/or preg are used, the value provided on this port is qualified by the rising edge of clk, subject to the appropriate register controls. bcin[17:0] input the second 18-bit two?s complement value for multiplication if the b_input attribute is set to cascade. the block multiplies by this value asynchronously if the optional breg and preg registers are omitted. when breg and/or preg are used, the value provided on this port is qualified by the rising edge of clk, subject to the appropriate register controls. p[35:0] output the 36-bit two?s complement product resulting from the multiplication of the two input values applied to the multiplier. if the optional areg, breg and preg registers are omitted, the output operates asynchronously. use of preg causes this output to respond to the rising edge of clk with the value qualified by cep and rstp. if preg is omitted, but areg and breg are used, this output responds to the rising edge of clk with the value qualified by cea, rsta, ceb, and rstb. if preg is omitted and only one of areg or breg is used, this output responds to both asynchronous and synchronous events. bcout[17:0] output the value being applied to the second input of the multiplier. when the optional breg register is omitted, this output responds asynchronously in response to changes at the b[17:0] or bcin[17:0] ports according to the setting of the b_input attribute. if breg is used, this output responds to the rising edge of clk with the value qualified by ceb and rstb. cea input clock enable qualifier for the optional areg register. the value provided on the a[17:0] port is captured by areg in response to a rising edge of clk when this signal is high, provided that rsta is low. rsta input synchronous reset for the optional areg register. areg content is forced to the value zero in response to a rising edge of clk when this signal is high. ceb input clock enable qualifier for the optional breg register. the value provided on the b[17:0] or bcin[17:0] port is captured by breg in response to a rising edge of clk when this signal is high, provided that rstb is low. rstb input synchronous reset for the optional breg register. breg content is forced to the value zero in response to a rising edge of clk when this signal is high. cep input clock enable qualifier for the optional preg register. the value provided on the output of the multiplier port is captured by preg in response to a rising edge of clk when this signal is high, provided that rstp is low. rstp input synchronous reset for the optional preg register. preg content is forced to the value zero in response to a rising edge of clk when this signal is high. notes: 1. the control signals clk, cea, rsta, ceb, rstb, cep, and rstp have the option of inverted polarity. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 39 advance product specification r digital clock managers (dcms) differences from the spartan-3 architecture spartan-3e fpgas have two, four, or eight dcms, depending on device size. the spartan-3e dcm has a maximum phase shift range of 180. the spartan-3 dcm range is 360. the spartan-3e dll supports lower input frequencies, down to 5 mhz. spartan-3 dlls supports down to 24 mhz. overview spartan-3e digital clock managers (dcms) provide flexi- ble, complete control over clock frequency, phase shift and skew. to accomplish this, the dcm employs a delay-locked loop (dll), a fully digital control system that uses feedback to maintain clock signal characteristics with a high degree of precision despite normal variations in operating tempera- ture and voltage. this section provides a fundamental description of the dcm. see x app462 : "using digital clock managers (dcms) in spartan-3 series fpgas" for further information. the XC3S100E fpga has two dcms, one at the top and one at the bottom of the device. the xc3s250e and xc3s500e fpgas each include four dcms, two at the top and two at the bottom. the xc3s1200e and xc3s1600e fpgas contain eight dcms with two on each edge (see also figure 42 ). the dcm in spartan-3e fpgas is sur- rounded by clbs within the logic array and is no longer located at the top and bottom of a column of block ram as in the spartan-3 architecture,. the digital clock manager is instantiated into a design as the ?dcm? primitive. the dcm supports three major functions: clock-skew elimination: clock skew describes the extent to which clock signals may, under normal circumstances, deviate from zero-phase alignment. it occurs when slight differences in path delays cause the clock signal to arrive at different points on the die at different times. this clock skew can increase set-up and hold time requirements as well as clock-to-out time, which may be undesirable in applications operating at a high frequency, when timing is critical. the dcm eliminates clock skew by aligning the output clock signal it generates with another version of the clock signal that is fed back. as a result, the two clock signals establish a zero-phase relationship. this effectively cancels out clock distribution delays that might lie in the signal path leading from the clock output of the dcm to its feedback input. frequency synthesis: provided with an input signal, the dcm can generate a wide range of different output clock frequencies. this is accomplished by either multiplying and/or dividing the frequency of the input clock signal by any of several different factors. phase shifting: the dcm provides the ability to shift the phase of all its output clock signals with respect to its input clock signal. the dcm has four functional components: the delay-locked loop (dll), the digital frequency synthe- sizer (dfs), the phase shifter (ps), and the status logic. each component has its associated signals, as shown in figure 37 . figure 37: dcm functional blocks and associated signals ds099-2_07_040103 psincdec psen psclk clkin clkfb rst status [7:0] locked 8 clkfx180 clkfx clk0 psdone clock distribution delay clk90 clk180 clk270 clk2x clk2x180 clkdv status logic dfs dll phase shifter delay taps output stage input stage dcm functional description 40 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r delay-locked loop (dll) the most basic function of the dll component is to elimi- nate clock skew. the main signal path of the dll consists of an input stage, followed by a series of discrete delay ele- ments or taps, which in turn leads to an output stage. this path together with logic for phase detection and control forms a system complete with feedback as shown in figure 38 . in spartan-3e fpgas, the dll is implemented using a counter-based delay line. the dll component has two clock inputs, clkin and clkfb, as well as seven clock outputs, clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv as described in ta b l e 2 5 . the clock outputs drive simulta- neously. signals that initialize and report the state of the dll are discussed in the status logic component section. the clock signal supplied to the clkin input serves as a reference waveform. the dll seeks to align the rising-edge of feedback signal at the clkfb input with the rising-edge of clkin input. when eliminating clock skew, the common approach to using the dll is as follows: the clk0 signal is passed through the clock distribution network to all the reg- isters it synchronizes. these registers are either internal or external to the fpga. after passing through the clock distri- bution network, the clock signal returns to the dll via a feedback line called clkfb. the control block inside the dll measures the phase error between clkfb and clkin. figure 38: simplified functional diagram of dll ds099-2_08_041103 clkin delay n clkfb rst clk0 clk90 clk180 clk270 clk2x clk2x180 clkdv output section control delay n-1 phase detection locked delay 2 delay 1 table 25: dll signals signal direction description clkin input accepts original clock signal. clkfb input accepts either clk0 or clk2x as the feedback signal. (set clk_feedback attribute accordingly). clk0 output generates a clock signal with same frequency and phase as clkin. clk90 output generates a clock signal with same frequency as clkin, only phase-shifted 90. clk180 output generates a clock signal with same frequency as clkin, only phase-shifted 180. clk270 output generates a clock signal with same frequency as clkin, only phase-shifted 270. clk2x output generates a clock signal with same phase as clkin, only twice the frequency. clk2x180 output generates a clock signal with twice the frequency of clkin, phase-shifted 180 with respect to clkin. clkdv output divides the clkin frequency by clkdv_divide value to generate lower frequency clock signal that is phase-aligned to clkin. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 41 advance product specification r this phase error is a measure of the clock skew that the clock distribution network introduces. the control block acti- vates the appropriate number of delay elements to cancel out the clock skew. once the dll has brought the clk0 sig- nal in phase with the clkin signal, it asserts the locked output, indicating a lock on to the clkin signal. dll attributes and related functions a number of different functional options can be set for the dll component through the use of the attributes described in ta b l e 2 6 . each attribute is described in detail in the sec- tions that follow: dll clock input connections an external clock source enters the fpga using a global clock input buffer (ibufg), which directly accesses the glo- bal clock network or via an input buffer (ibuf). clock sig- nals within the fpga drive a global clock net using a global clock multiplexer buffer (bufgmux). the global clock net connects directly to the clkin input. the internal and exter- nal connections are shown in figure 39a and figure 39c , respectively. a differential clock (e.g., lvds) can serve as an input to clkin. dll clock output and feedback connections as many as four of the nine dcm clock outputs can simulta- neously drive four of the bufgmux buffers on the same die edge. all dcm clock outputs can simultaneously drive gen- eral routing resources, including interconnect leading to obuf buffers. the feedback loop is essential for dll operation and is established by driving the clkfb input with either the clk0 or the clk2x signal so that any undesirable clock distribu- tion delay is included in the loop. it is possible to use either of these two signals for synchronizing any of the seven dll outputs: clk0, clk90, clk180, clk270, clkdv, clk2x, or clk2x180. the value assigned to the clk_feedback attribute must agree with the physical feedback connection: a value of 1x for the clk0 case, 2x for the clk2x case. if the dcm is used in an application that does not require the dll ? that is, only the dfs is used ? then there is no required feedback loop so clk_feedback is set to none. there are two basic cases that determine how to connect the dll clock outputs and feedback connections: on-chip synchronization and off-chip synchronization, which are illustrated in figure 39a through figure 39d . table 26: dll attributes attribute description values clk_feedback chooses either the clk0 or clk2x output to drive the clkfb input none, 1x, 2x clkin_divide_by_2 halves the frequency of the clkin signal just as it enters the dcm true, false clkdv_divide selects the constant used to divide the clkin input frequency to generate the clkdv output frequency 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16 duty_cycle_correction enables 50% duty cycle correction for the clk0, clk90, clk180, and clk270 outputs true, false functional description 42 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r in the on-chip synchronization case in figure 39a and figure 39b , it is possible to connect any of the dll?s seven output clock signals through general routing resources to the fpga?s internal registers. either a global clock buffer (bufg) or a bufgmux affords access to the global clock network. as shown in figure 39a , the feedback loop is cre- ated by routing clk0 (or clk2x, in figure 39b to a global clock net, which in turn drives the clkfb input. in the off-chip synchronization case in figure 39c and figure 39d , clk0 (or clk2x) plus any of the dll?s other output clock signals exit the fpga using output buffers (obuf) to drive an external clock network plus registers on the board. as shown in figure 39c , the feedback loop is formed by feeding clk0 (or clk2x, in figure 39d ) back into the fpga using an ibufg, which directly accesses the global clock network, or an ibuf. then, the global clock net is connected directly to the clkfb input. accommodating high input frequencies if the frequency of the clkin signal is high such that it exceeds the maximum permitted, divide it down to an acceptable value using the clkin_divide_by_2 attribute. when this attribute is set to true, the clkin frequency is divided by a factor of two just as it enters the dcm. coarse phase shift outputs of the dll compo- nent in addition to clk0 for zero-phase alignment to the clkin signal, the dll also provides the clk90, clk180, and clk270 outputs for 90, 180, and 270 phase-shifted sig- nals, respectively. these signals are described in ta bl e 2 5 . their relative timing is shown in figure 40 . for control in finer increments than 90, see phase shifter (ps) . basic frequency synthesis outputs of the dll component the dll component provides basic options for frequency multiplication and division in addition to the more flexible synthesis capability of the dfs component, described in a later section. these operations result in output clock signals with frequencies that are either a fraction (for division) or a multiple (for multiplication) of the incoming clock frequency. the clk2x output produces an in-phase signal that is twice the frequency of clkin. the clk2x180 output also dou- bles the frequency, but is 180 out-of-phase with respect to clkin. the clkdiv output generates a clock frequency that is a predetermined fraction of the clkin frequency. the clkdv_divide attribute determines the factor used to divide the clkin frequency. the attribute can be set to var- figure 39: input clock, output clock, and feedback connections for the dll ds099-2_09_082104 clk90 clk180 clk270 clkdv clk2x clk2x180 clk0 clk0 clock net delay bufgmux bufgmux bufg fpga (a) on-chip with clk0 feedback clkin dcm clkfb clk90 clk180 clk270 clkdv clk2x clk2x180 clk0 clk0 clock net delay ibufg ibufg fpga (c) off-chip with clk0 feedback clkin dcm clkfb obuf obuf clk2x clk2x ibufg ibufg fpga (d) off-chip with clk2x feedback clkin dcm clkfb obuf obuf clk0 clk90 clk180 clk270 clkdv clk2x180 clk2x clk2x clock net delay clock net delay bufgmux bufgmux bufg fpga (b) on-chip with clk2x feedback clkin dcm clkfb clk0 clk90 clk180 clk270 clkdv clk2x180 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 43 advance product specification r ious values as described in ta b l e 2 6 . the basic frequency synthesis outputs are described in ta bl e 2 5 . duty cycle correction of dll clock outputs the clk2x (1) , clk2x180, and clkdv (2) output signals ordinarily exhibit a 50% duty cycle ? even if the incoming clkin signal has a different duty cycle. fifty-percent duty cycle means that the high and low times of each clock cycle are equal. the duty_cycle_correction attribute determines whether or not duty cycle correction is applied to the clk0, clk90, clk180, and clk270 outputs. if duty_cycle_correction is set to true, then the duty cycle of these four outputs is corrected to 50%. if duty_cycle_correction is set to false, then these outputs exhibit the same duty cycle as the clkin signal. figure 40 compares the characteristics of the dll?s output signals to those of the clkin signal. the clk2x output generates a 25% duty cycle clock at the same frequency as the clkin signal until the dll has achieved lock. the duty cycle of the clkdv outputs may differ somewhat from 50% (i.e., the signal is high for less than 50% of the period) when the clkdv_divide attribute is set to a non-integer value and the dll is operating in the high fre- quency mode. digital frequency synthesizer (dfs) the dfs component generates clock signals the frequency of which is a product of the clock frequency at the clkin input and a ratio of two user-determined integers. because of the wide range of possible output frequencies such a ratio permits, the dfs feature provides still further flexibility than the dll?s basic synthesis options as described in the pre- ceding section. the dfs component?s two dedicated out- puts, clkfx and clkfx180, are defined in ta bl e 2 8 . the signal at the clkfx180 output is essentially an inver- sion of the clkfx signal. these two outputs always exhibit a 50% duty cycle. this is true even when the clkin signal does not. these dfs clock outputs are driven at the same time as the dll?s seven clock outputs. the numerator of the ratio is the integer value assigned to the attribute clkfx_multiply and the denominator is the integer value assigned to the attribute clkfx_divide. these attributes are described in ta bl e 2 7 . the output frequency (f clkfx ) can be expressed as a func- tion of the incoming clock frequency (f clkin ) as follows: f clkfx = f clkin *(clkfx_multiply/clkfx_divide) (3) regarding the two attributes, it is possible to assign any combination of integer values, provided that two conditions are met: 1. the two values fall within their corresponding ranges, as specified in ta b l e 2 7 . 2. the f clkfx frequency calculated from the above expression accords with the dcm?s operating frequency specifications. for example, if clkfx_multiply = 5 and clkfx_divide = 3, then the frequency of the output clock signal is 5/3 that of the input clock signal. dfs with or without the dll the dfs component can be used with or without the dll component: without the dll, the dfs component multi- plies or divides the clkin signal frequency according to the respective clkfx_multiply and clkfx_divide values, figure 40: characteristics of the dll clock outputs output signal - duty cycle is always corrected output signal - attribute corrects duty cycle phase: input signal (30% duty cycle) 0 o 90 o 180 o 270 o 0 o 90 o 180 o 270 o 0 o duty_cycle_correction = false duty_cycle_correction = true ds099-2_10_031303 clk2x clk2x180 clkin clkdv (1) clk0 clk90 clk180 clk270 clk0 clk90 clk180 clk270 t functional description 44 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r generating a clock with the new target frequency on the clkfx and clkfx180 outputs. though classified as belonging to the dll component, the clkin input is shared with the dfs component. this case does not employ feed- back loop. therefore, it cannot correct for clock distribution delay. with the dll, the dfs operates as described in the preced- ing case, only with the additional benefit of eliminating the clock distribution delay. in this case, a feedback loop from the clk0 output to the clkfb input must be present. the dll and dfs components work together to achieve this phase correction as follows: given values for the clkfx_multiply and clkfx_divide attributes, the dll selects the delay element for which the output clock edge coincides with the input clock edge whenever mathemati- cally possible. for example, when clkfx_multiply = 5 and clkfx_divide = 3, the input and output clock edges coincide every three input periods, which is equivalent in time to five output periods. smaller clkfx_multiply and clkfx_divide values achieve faster lock times. with no factors common to the two attributes, alignment occurs once with every number of cycles equal to the clkfx_divide value. therefore, it is recommended that the user reduce these values by factor- ing wherever possible. for example, given clkfx_multiply = 9 and clkfx_divide = 6, removing a factor of three yields clkfx_multiply = 3 and clkfx_divide = 2. while both value-pairs result in the multiplication of clock frequency by 3/2, the latter value-pair enables the dll to lock more quickly. dfs clock output connections there are two basic cases that determine how to connect the dfs clock outputs: on-chip and off-chip, which are illus- trated in figure 39a and figure 39c , respectively. this is similar to what has already been described for the dll com- ponent. see dll clock output and feedback connec- tions . in the on-chip case, it is possible to connect either of the dfs?s two output clock signals through general routing resources to the fpga?s internal registers. either a global clock buffer (bufg) or a bufgmux affords access to the global clock network. the optional feedback loop is formed in this way, routing clk0 to a global clock net, which in turn drives the clkfb input. in the off-chip case, the dfs?s two output clock signals, plus clk0 for an optional feedback loop, can exit the fpga using output buffers (obuf) to drive a clock network plus registers on the board. the feedback loop is formed by feeding the clk0 signal back into the fpga using an ibufg, which directly accesses the global clock network, or an ibuf. then the global clock net is connected directly to the clkfb input. phase shifter (ps) the dcm provides two approaches to controlling the phase of a dcm clock output signal relative to the clkin signal: first, there are nine clock outputs that employ the dll to achieve a desired phase relationship: clk0, clk90, clk180, clk270, clk2x, clk2x180, clkdv clkfx, and clkfx180. these outputs afford ?coarse? phase control. the second approach uses the ps component described in this section to provide a still finer degree of control. the ps component accomplishes this by introducing a "fine phase shift" (t ps ) between the clkfb and clkin signals inside the dll component. the user can control this fine phase shift down to a resolution of 1/512 of a clkin cycle or one tap delay (dcm_tap), whichever is greater. when in use, the ps component shifts the phase of all nine dcm clock output signals together. if the ps component is used together with a dcm clock output such as the clk90, clk180, clk270, clk2x180, and clkfx180, then the fine phase shift of the former gets added to the coarse phase shift of the latter. ps component enabling and mode selection the clkout_phase_shift attribute enables the ps component for use in addition to selecting between two operating modes. as described in ta b l e 2 9 , this attribute has three possible values: none, fixed, and variable. when clkout_phase_shift is set to none, the ps component is disabled and its inputs, psen, psclk, and psincdec, must be tied to gnd. the set of waveforms in figure 41a shows the disabled case, where the dll main- tains a zero-phase alignment of signals clkfb and clkin upon which the ps component has no effect. the ps com- table 27: dfs attributes attribute description values clkfx_multiply frequency multiplier constant integer from 2 to 32, inclusive clkfx_divide frequency divisor constant integer from 1 to 32, inclusive table 28: dfs signals signal direction description clkfx output multiplies the clkin frequency by the attribute-value ratio (clkfx_multiply/ clkfx_divide) to generate a clock signal with a new target frequency. clkfx180 output generates a clock signal with same frequency as clkfx, only shifted 180 out-of-phase. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 45 advance product specification r ponent is enabled by setting the attribute to either the fixed or variable values, which select the fixed phase mode and the variable phase mode, respectively. these two modes are described in the sections that follow. determining the fine phase shift the user controls the phase shift of clkfb relative to clkin by setting and/or adjusting the value of the phase_shift attribute. this value must be an integer ranging from ?255 to +255. this corresponds to a phase shift range of ?180 to +180 degrees, which is different from the original spartan-3 dcm. the ps component uses this value to calculate the desired fine phase shift (t ps ) as a fraction of the clkin period (t clkin ). given values for phase_shift and t clkin , it is possible to calculate t ps as follows: t ps = (phase_shift/512) * t clkin (4) both the fixed phase and variable phase operating modes employ this calculation. if the phase_shift value is zero, then clkfb and clkin are in phase, the same as when the ps component is disabled. when the phase_shift value is positive, the clkfb signal is shifted later in time with respect to clkin. if the attribute value is negative, the clkfb signal is shifted earlier in time with respect to clkin. the fixed phase mode this mode fixes the desired fine phase shift to a fraction of the t clkin , as determined by equation (4) and its user-selected phase_shift value p. the set of wave- forms in figure 41b illustrates the relationship between clkfb and clkin in the fixed phase mode. in the fixed phase mode, the psen, psclk, and psincdec inputs are not used and must be tied to gnd. in figure 41 : p represents the integer value ranging from ?255 to +255 to which the phase_shift attribute is assigned. (p = approximately -90 as shown) n is an integer value ranging from (p ? 255) to (+255 ? p) that represents the net phase shift effect from a series of increment and/or decrement operations. n = {total number of increments} ? {total number of decrements} provided the user does not try to increment past + 255 or decrement past -255. a positive value for n indicates a net increment; a negative value indicates a net decrement. table 29: ps attributes attribute description values clkout_phase_shift disables the ps component or chooses between fixed phase and variable phase modes. none, fixed, variable phase_shift determines size and direction of initial fine phase shift. integers from ?255 to +255 functional description 46 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the variable phase mode the variable phase mode dynamically adjusts the fine phase shift over time using three inputs to the ps compo- nent (psen, psclk, and psincdec), as defined in table 30 . figure 41: phase shifter waveforms ds312-2_61_021505 clkin clkfb * t clkin p 512 b. clkout_phase_shift = fixed * t clkin p 512 shift range over all p values: ?55 +255 shift range over all p values: 0 0 ?55 +255 shift range over all n values: clkin clkfb before increment c. clkout_phase_shift = variable clkfb after increment * t clkin n 512 clkin clkfb a. clkout_phase_shift = none table 30: signals for variable phase mode signal direction description psen (1) input enables psclk for variable phase adjustment. psclk (1) input clock to synchronize phase shift adjustment. psincdec (1) input chooses between increment and decrement for phase adjustment. it is synchronized to the psclk signal. psdone output goes high to indicate that present phase adjustment is complete and ps component is ready for next phase adjustment request. it is synchronized to the psclk signal. notes: 1. it is possible to program this input for either a true or inverted polarity. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 47 advance product specification r just following device configuration, the ps component ini- tially determines t ps by evaluating equation (4) for the value assigned to the phase_shift attribute. then to dynamically adjust that phase shift, use the three ps inputs to increase or decrease the fine phase shift. psincdec is synchronized to the psclk clock signal, which is enabled by asserting psen. it is possible to drive the psclk input with the clkin signal or any other clock signal. a request for phase adjustment is entered as follows: for each psclk cycle that psincdec is high, the ps component adds 1/512 of a clkin cycle to t ps . similarly, for each enabled psclk cycle that psincdec is low, the ps component subtracts 1/512 of a clkin cycle from t ps . the phase adjustment may require as many as 100 clkin cycles plus three psclk cycles to take effect, at which point the output psdone goes high for one psclk cycle. this pulse indicates that the ps component has finished the present adjustment and is now ready for the next request. asserting the reset (rst) input, returns t ps to its original shift time, as determined by the phase_shift attribute value. the set of waveforms in figure 41c illustrates the relationship between clkfb and clkin in the variable phase mode. the status logic component the status logic component not only reports on the state of the dcm but also provides a means of resetting the dcm to an initial known state. the signals associated with the sta- tus logic component are described in ta bl e 3 1 . as a rule, the reset (rst) input is asserted only upon con- figuring the device or changing the clkin frequency. a dcm reset does not affect attribute values (e.g., clkfx_multiply and clkfx_divide). if not used, tie rst to gnd. the eight bits of the status bus are defined in ta b l e 3 2 . table 31: status logic signals signal direction description rst input a high resets the entire dcm to its initial power-on state. initializes the dll taps for a delay of zero. sets the locked output low. this input is asynchronous. status[7:0] output the bit values on the status bus provide information regarding the state of dll and ps operation locked output indicates that the clkin and clkfb signals are in phase by going high. the two signals are out-of-phase when low. table 32: dcm status bus bit name description 0 reserved - 1 clkin stopped a value of 1 indicates that the clkin input signal is not toggling. a value of 0 indicates toggling. this bit functions only when the clkfb input is connected. (1) 2 clkfx stopped a value of 1 indicates that the clkfx output is not toggling. a value of 0 indicates toggling. this bit functions only when the clkfx or clkfx180 output are connected. 3-6 reserved - notes: 1. if only the dfs clock outputs are used, but none of the dll clock outputs, this bit does not go high when the clkin signal st ops. functional description 48 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r stabilizing dcm clocks before user mode the startup_wait attribute shown in ta b l e 3 3 optionally delays the end of the fpga?s configuration process until after the dcm locks to the incoming clock frequency. this option ensures that the fpga remains in the startup phase of configuration until all clock outputs generated by the dcm are stable. when all the dcms with their startup_wait attribute set to true assert the locked signal, then the fpga completes its configuration process and proceeds to user mode. the associated bitstream gen- erator (bitgen) option lck_cycle specifies one of the six cycles in the startup phase. the selected cycle defines the point at which configuration halts until the all the locked outputs go high. also see start-up , page 91 . clocking infrastructure the spartan-3e clocking infrastructure, shown in figure 42 , provides a series of low-capacitance, low-skew interconnect lines well-suited to carrying high-frequency signals through- out the fpga. the infrastructure also includes the clock inputs and bufgmux clock buffers/multiplexers. the xilinx place-and-route (par) software automatically routes high-fanout clock signals using these resources. clock inputs clock pins accept external clock signals and connect directly to dcms and bufgmux elements. each spartan-3e fpga has: 16 global clock inputs (gclk0 through gclk15) located along the top and bottom edges of the fpga 8 right-half clock inputs (rhclk0 through rhclk7) located along the right edge 8 left-half clock inputs (lhclk0 through lhclk7) located along the left edge clock inputs optionally connect directly to dcms using ded- icated connections. ta b l e 3 5 shows the clock inputs that feed a specific dcm within a given spartan-3e part number. different spartan-3e fpga densities have different num- bers of dcms. each clock input is also optionally a user-i/o pin and con- nects to internal interconnect. some clock pad pins are input-only pins as indicated in module 4 of the spartan-3e data sheet. clock buffers/multiplexers clock buffers/multiplexers either drive clock input signals directly onto a clock line (bufg) or optionally provide a mul- tiplexer to switch between two unrelated, possibly asynchro- nous clock signals (bufgmux). each bufgmux element, shown in figure 43 , is a 2-to-1 multiplexer. the select line, s, chooses which of the two inputs, i0 or i1, drives the bufgmux?s output signal, o, as described in ta b l e 3 4 . the switching from one clock to the other is glitch-less, and done in such a way that the output high and low times are never shorter than the shortest high or low time of either input clock. the bufg clock buffer primitive drives a single clock signal onto the clock network and is essentially the same element as a bufgmux, just without the clock select mechanism. similarly, the bufgce primitive creates an enabled clock buffer using the bufgmux select mechanism. the i0 and i1 inputs to an bufgmux element originate from clock input pins, dcms, or double-line interconnect, as shown in figure 43 . as shown in figure 42 , there are 24 bufgmux elements distributed around the four edges of the device. clock signals from the four bufgmux elements at the top edge and the four at the bottom edge are truly glo- bal and connect to all clocking quadrants. the eight left-edge bufgmux elements only connect to the two clock quadrants in the left half of the device. similarly, the eight right-edge bufgmux elements only connect to the right half of the device. bufgmux elements are organized in pairs and share i0 and i1 connections with adjacent bufgmux elements from a common clock switch matrix as shown in figure 43 . for example, the input on i0 of one bufgmux also a shared input to i1 of the adjacent bufgmux. the clock switch matrix for the left- and right-edge bufg- mux elements receive signals from any of the three follow- ing sources: an lhclk or rhclk pin as appropriate, a double-line interconnect, or a dcm in the xc3s1200e and xc3s1600e devices. by contrast, the clock switch matrixes on the top and bottom edges receive signals from any of the five following sources: two gclk pins, two dcm outputs, or one double-line inter- connect. ta b l e 3 6 indicates permissible connections between clock inputs and bufgmux elements. the four bufgmux ele- ments on the top edge are paired together and share inputs from the eight global clock inputs along the top edge. each table 33: startup_wait attribute attribute description values startup_wait delays transition from configuration to user mode until dcm locks to input clock. true, false table 34: bufgmux select mechanism s input o output 0 i0 input 1 i1 input functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 49 advance product specification r bufgmux pair connects to four of the eight global clock inputs, as shown in figure 42 . this optionally allows differ- ential inputs to the global clock inputs without wasting a bufgmux element. the connections for the bottom-edge bufgmux elements is similar to the top-edge connections. on the left and right edges, only two clock inputs feed each pair of bufgmux elements. figure 42: spartan-3e internal quadrant-based clock network (top view) 8 8 88 4 8 8 8 8 left spine top left quadrant (tl) top right quadrant (tr) bottom right quadrant (br) bottom left quadrant (bl) right spine horizontal spine top spine bottom spine 4 ds312-2_04_030205 dcm xc3s250e (x0y1) xc3s500e (x0y1) xc3s1200e (x1y3) xc3s1600e (x1y3) 4 4 dcm xc3s250e (x0y0) xc3s500e (x0y0) xc3s1200e (x1y0) xc3s1600e (x1y0) 4 4 4 4 4 dcm XC3S100E (x0y1) xc3s250e (x1y1) xc3s500e (x1y1) xc3s1200e (x2y3) xc3s1600e (x2y3) 4 dcm XC3S100E (x0y0) xc3s250e (x1y0) xc3s500e (x1y0) xc3s1200e (x2y0) xc3s1600e (x2y0) x1y10 x1y11 x2y10 x2y11 gclk6 gclk10 gclk7 gclk11 gclk4 gclk8 gclk5 gclk9 x1y0 x1y1 x2y0 x2y1 gclk15 gclk3 gclk14 gclk2 gclk13 gclk1 gclk12 gclk0 x0y6 x0y7 x0y8 x0y9 lhclk2 lhclk3 lhclk0 lhclk1 x0y2 x0y3 x0y4 x0y5 lhclk6 lhclk7 lhclk4 lhclk5 x3y5 x3y4 x3y3 x3y2 rhclk2 rhclk3 rhclk0 rhclk1 x3y9 x3y8 x3y7 x3y6 rhclk6 rhclk7 rhclk4 rhclk5 4 4 4 4 4 4 4 4 4 4 4 4 dcm xc3s1200e (x0y2) xc3s1600e (x0y2) 4 4 4 4 dcm xc3s1200e (x0y1) xc3s1600e (x0y1) dcm xc3s1200e (x3y1) xc3s1600e (x3y1) dcm xc3s1200e (x3y2) xc3s1600e (x3y2) global clock inputs global clock inputs left-half clock inputs right-half clock inputs bufgmux bufgmux h g b a d c f e a c h g b a d c f e b d e gf h pair clock line in quadrant figure 44a figure 44a figure 44b figure 44b notes: 1. number of dcms and locations of these dcm varies for different device densities. 2. the left and right dcms are only in the xc3s1200e and xc3s1600e. the XC3S100E has only two dcms, one on the top right and one on the bottom right of the die. functional description 50 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r table 35: direct connections from clock inputs to dcms and associated dcm location string clock input XC3S100E xc3s250e/xc3s500e xc3s1200e/xc3s1600e gclk[3:0] dcm_x0y0 dcm_x1y0 dcm_x2y0 rhclk[3:0] n/a n/a dcm_x3y1 rhclk[7:4] n/a n/a dcm_x3y2 gclk[7:4] dcm_x0y1 dcm_x1y1 dcm_x2y2 gclk[11:8] n/a dcm_x0y1 dcm_x1y3 lhclk[3:0] n/a n/a dcm_x0y2 lhclk[7:4] n/a n/a dcm_x0y1 gclk[15:12] n/a dcm_x0y0 dcm_x1y0 table 36: connections from clock inputs to bufgmux elements and associated quadrant clock quadrant clock line (1) left-half bufgmux top or bottom bufgmux right-half bufgmux location (2) i0 input i1 input location (2) i0 input i1 input location (2) i0 input i1 input a x0y2 lhclk7 lhclk6 x2y1 gclk0 or gclk12 gclk1 or gclk13 x3y2 rhclk0 rhclk1 b x0y3 lhclk6 lhclk7 x2y0 gclk1 or gclk13 gclk0 or gclk12 x3y3 rhclk1 rhclk0 c x0y4 lhclk5 lhclk4 x1y1 gclk2 or gclk14 gclk3 or gclk15 x3y4 rhclk2 rhclk3 d x0y5 lhclk4 lhclk5 x1y0 gclk3 or gclk15 gclk2 or gclk14 x3y5 rhclk3 rhclk2 e x0y6 lhclk3 lhclk2 x2y11 gclk4 or gclk8 gclk5 or gclk9 x3y6 rhclk4 rhclk5 f x0y7 lhclk2 lhclk3 x2y10 gclk5 or gclk9 gclk4 or gclk8 x3y7 rhclk5 rhclk4 g x0y8 lhclk1 lhclk0 x1y11 gclk6 or gclk10 gclk7 or gclk11 x3y8 rhclk6 rhclk7 h x0y9 lhclk0 lhclk1 x1y10 gclk7 or gclk11 gclk6 or gclk10 x3y9 rhclk7 rhclk6 notes: 1. see quadrant clock routing for connectivity details for the eight quadrant clocks. 2. see figure 42 for specific bufgmux locations and figure 44 for information on how bufgmux elements drive onto a specific clock line within a quadrant. functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 51 advance product specification r quadrant clock routing the clock routing within the fpga is quadrant-based, as shown in figure 42 . each clock quadrant supports eight total clock signals, labeled ?a? through ?h? in ta b l e 3 6 and figure 44 . the clock source for an individual clock line orig- inates either from a global bufgmux element along the top and bottom edges or from a bufgmux element along the associated edge, as shown in figure 44 . the clock lines feed the synchronous resource elements (clbs, iobs, block ram, multipliers, and dcms) within the quadrant. the four quadrants of the device are: top right (tr) bottom right (br) bottom left (bl) top left (tl) note that the quadrant clock notation (tr, br, bl, tl) is separate from that used for similar iob placement con- straints. figure 43: clock switch matrix to bufgmux pair connectivity bufgmux lhclk or rhclk input double line dcm output* left-/right-half bufgmux clk switch matrix s o o s i1 i0 i1 i0 bufgmux top/bottom (global) bufgmux clk switch matrix s o o s i1 i0 i1 i0 1st gclk pin 2nd gclk pin 1st dcm output 2nd dcm output double line ds312-2_16_022505 0 1 0 1 0 1 0 1 *(xc3s1200e and and xc3s1600e only) functional description 52 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the outputs of the top or bottom bufgmux elements con- nect to two vertical spines, each comprising four vertical clock lines as shown in figure 42 . at the center of the die, these clock signals connect to the eight-line horizontal clock spine. outputs of the left and right bufgmux elements are routed onto the left or right horizontal spines, each comprising eight horizontal clock lines. each of the eight clock signals in a clock quadrant derives either from a global clock signal or a half clock signal. in other words, there are up to 24 total potential clock inputs to the fpga, eight of which can connect to clocked elements in a single clock quadrant. figure 44 shows how the clock lines in each quadrant are selected from associated bufg- mux sources. for example, if quadrant clock ?a? in the bot- tom left (bl) quadrant originates from bufgmux_x2y1, then the clock signal from bufgmux_x0y2 is unavailable in the bottom left quadrant. however, the top left (tl) quad- rant clock ?a? can still solely use the output from either bufgmux_x2y1 or bufgmux_x0y2 as the source. to minimize the dynamic power dissipation of the clock net- work, the xilinx development software automatically dis- ables all clock segments not in use. figure 44: clock sources for the eight clock lines within a clock quadrant x2y1 (global) a b c d e f g h x0y2 (left half) x2y0 (global) x0y3 (left half) x1y1 (global) x0y4 (left half) x1y0 (global) x0y5 (left half) x2y11 (global) x0y6 (left half) x2y10 (global) x0y7 (left half) x1y11 (global) x0y8 (left half) x1y10 (global) x0y9 (left half) bufgmux output clock line x2y1 (global) a b c d e f g h x3y2 (right half) x2y0 (global) x3y3 (right half) x1y1 (global) x3y4 (right half) x1y0 (global) x3y5 (right half) x2y11 (global) x3y6 (right half) x2y10 (global) x3y7 (right half) x1y11 (global) x3y8 (right half) x1y10 (global) x3y9 (right half) bufgmux output ds312-2_17_030105 a. left (tl and bl quadrants) half of die b. right (tr and br quadrants) half of die clock line functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 53 advance product specification r interconnect interconnect is the programmable network of signal path- ways between the inputs and outputs of functional elements within the fpga, such as iobs, clbs, dcms, block ram, etc. interconnect, also called routing, is segmented for optimal connectivity. functionally, interconnect resources are identi- cal to that of the spartan-3 architecture. there are four kinds of interconnects: long lines, hex lines, double lines, and direct lines. the xilinx place and route (par) software exploits the rich interconnect array to deliver optimal system performance and the fastest compile times. the switch matrix connects to the different kinds of intercon- nects across the device. an interconnect tile, shown in figure 45 , is defined as a single switch matrix connected to a functional element, such as a clb, iob, or dcm. if a func- tional element spans across multiple switch matrices such as the block ram or multipliers, then an interconnect tile is defined by the number of switch matrices connected to that functional element. a spartan-3e device can be repre- sented as an array of interconnect tiles where interconnect resources are for the channel between any two adjacent interconnect tile rows or columns as shown in figure 46 . figure 45: four types of interconnect tiles (clbs, iobs, dcms, and block ram/multiplier) switch matrix switch matrix switch matrix switch matrix switch matrix clb 18kb block ram mult 18 x 18 switch matrix iob switch matrix dcm ds312_08_020905 figure 46: array of interconnect tiles in spartan-3e fpga switch matrix iob switch matrix iob switch matrix iob switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb iob clb clb clb clb switch matrix switch matrix ds312_09_020905 functional description 54 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r there are four type of general-purpose interconnect avail- able in each channel, as shown in figure 47 and described below. long lines each set of 24 long line signals spans the die both horizon- tally and vertically and connects to one out of every six inter- connect tiles. at any tile, four of the long lines drive or receive signals from a switch matrix. because of their low capacitance, these lines are well-suited for carrying high-frequency signals with minimal loading effects (e.g. skew). if all global clock lines are already committed and additional clock signals remain to be assigned, long lines serve as a good alternative. hex lines each set of eight hex lines are connected to one out of every three tiles, both horizontally and vertically. thirty-two hex lines are available between any given interconnect tile. hex lines are only driven from one end of the route. double lines each set of eight double lines are connected to every other tile, both horizontally and vertically. in all four directions. thirty-two double lines available between any given inter- connect tile. double lines are more connections and more flexibility, compared to long line and hex lines. direct connections direct connect lines route signals to neighboring tiles: verti- cally, horizontally, and diagonally. these lines most often drive a signal from a "source" tile to a double, hex, or long line and conversely from the longer interconnect back to a direct line accessing a "destination" tile. global controls (startup_spartan3e) in addition to the general-purpose interconnect, spartan-3e fpgas have two global logic control signals, as described in ta bl e 3 7 . these signals are available to the fpga appli- cation via the startup_spartan3e primitive. the global set/reset (gsr) signal replaces the global reset signal included in many asic-style designs. use the gsr control instead of a separate global reset signal in the design to free up clb inputs, resulting in a smaller, more efficient design. similarly, the gsr signal is asserted auto- matically during the fpga configuration process, guaran- teeing that the fpga starts-up in a known state. the startup_spartan3e primitive also includes two other signals used specifically during configuration. the mbt signals are for dynamically loading multiple con- figuration images using multiboot option , page 78 . the clk input is an alternate clock for configuration start-up , page 91 . table 37: spartan-3e global logic control signals global control input description gsr when driven high, asynchronously places all registers and flip-flops in their initial state (see initialization , page 24 ). asserted automatically during the fpga configuration process (see start-up , page 91 ). gts when driven high, asynchronously forces all i/o pins to a high-impedance state (hi-z, three-state). horizontal and vertical long lines (horizontal channel shown as an example) horizontal and vertical hex lines (horizontal channel shown as an example) figure 47: interconnect types between two adjacent interconnect tiles clb clb clb clb clb clb 66 666 clb clb clb clb ds312-2_10_022305 24 clb clb clb clb clb clb clb 8 ds312-2_11_020905 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 55 advance product specification r horizontal and vertical double lines (horizontal channel shown as an example) direct connections figure 47: interconnect types between two adjacent interconnect tiles clb 8 clb clb ds312-2_15_022305 clb clb clb clb clb clb clb clb clb ds312-2_12_020905 functional description 56 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r configuration differences from spartan-3 fpgas in general, spartan-3e fpga configuration modes are a superset to those available in spartan-3 fpgas. two new modes added in spartan-3e fpgas provide a glue-less configuration interface to industry-standard parallel nor flash and spi serial flash memories. unlike spartan-3 fpgas, nearly all of the spartan-3e configuration pins become available as user i/os after configuration. configuration process the function of a spartan-3e fpga is defined by loading application-specific configuration data into the fpga?s internal, reprogrammable cmos configuration latches (ccls), similar to the way a microprocessor?s function is defined by its application program. for fpgas, this configu- ration process uses a subset of the device pins, some of which are dedicated to configuration; other pins are merely borrowed and returned to the application as general-pur- pose user i/os after configuration completes. spartan-3e fpgas offer several configuration options to minimize the impact of configuration on the overall system design. in some configuration modes, the fpga generates a clock and loads itself from an external memory source, either serially or via a byte-wide data path. alternatively, an external host such as a microprocessor downloads the fpga?s configuration data using a simple synchronous serial interface or via a byte-wide peripheral-style interface. furthermore, multiple-fpga designs share a single config- uration memory source, creating a structure called a daisy chain. three fpga pins?m2, m1, and m0?select the desired configuration mode. the mode pin settings appear in ta b l e 3 8 . the mode pin values are sampled during the start of configuration when the fpga?s init_b output goes high. after the fpga completes configuration, the mode pins are available as user i/os. table 38: spartan-3e configuration mode pin settings master serial spi bpi slave parallel slave serial jtag m[2:0] mode pin settings <0:0:0> <0:0:1> <0:1:0>=up <0:1:1>=down <1:1:0> <1:1:1> <1:0:1> data width serial serial byte-wide byte-wide serial serial configuration memory source xilinx platform flash industry-standard spi serial flash industry-standard parallel nor flash any source via microcontroller, cpu, xilinx parallel platform flash , etc. any source via microcontroller, cpu, xilinx platform flash , etc. any source via microcontroller, cpu, etc. and system ace cf clock source internal oscillator internal oscillator internal oscillator external clock on cclk pin external clock on cclk pin external clock on tck pin total i/o pins borrowed during configuration 8 13 46 21 8 0 configuration mode for downstream daisy-chained fpgas slave serial slave serial slave parallel slave parallel or memory mapped slave serial jtag self-configuring applications (no external download host) possible using xcfxxp platform flash, which optionally generates cclk possible using xcfxxp platform flash, which optionally generates cclk uses low-cost, industry-standard flash functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 57 advance product specification r a specific spartan-3e part type always requires a constant number of configuration bits, regardless of design complex- ity, as shown in ta b l e 3 9 . the configuration file size for a multiple-fpga daisy-chain design equals the sum of the individual file sizes. pin behavior during configuration ta b l e 4 0 shows how various pins behave during the fpga configuration process. the actual behavior depends on the values applied to the m2, m1, and m0 mode select pins and the hswap pin. the mode select pins determine which of the i/o pins are borrowed during configuration and how they function. in jtag configuration mode, no user-i/o pins are borrowed for configuration. all i/o pins are high impedance (floating, three-stated, hi-z) during the configuration process. these pins are indicated in ta b l e 4 0 as shaded table entries or cells. if the hswap input is low, these pins have a pull-up resistor to their asso- ciated v cco supply that is active throughout configuration. after configuration, pull-up and pull-down resistors are available in the fpga application as described in pull-up and pull-down resistors , page 9 . spartan-3e fpgas have only six dedicated configuration pins, including the done and prog_b pins, and the four jtag boundary-scan pins: tdi, tdo, tms, and tck. table 39: number of bits to program a spartan-3e fpga (uncompressed bitstreams) device number of configuration bits XC3S100E 581,344 xc3s250e 1,352,192 xc3s500e 2,267,136 xc3s1200e 3,832,320 xc3s1600e 5,957,760 table 40: pin behavior during configuration pin name master serial spi (serial flash) bpi (parallel nor flash) jtag slave parallel slave serial supply/ i/o bank tdi tdi tdi tdi tdi tdi tdi vccaux tms tms tms tms tms tms tms vccaux tck tck tck tck tck tck tck vccaux tdo tdo tdo tdo tdo tdo tdo vccaux prog_b prog_b prog_b prog_b prog_b prog_b prog_b vccaux done done done done done done done vccaux hswap hswap hswap hswap hswap hswap hswap 0 m2 0 0 0 1 1 1 2 m1 0 0 1 0 1 1 2 m0 0 1 0 = up 1 = down 1 0 1 2 cclk cclk (o) cclk (o) cclk (o) cclk (i) cclk (i) 2 init_b init_b init_b init_b init_b init_b 2 cso_b cso_b cso_b cso_b 2 dout/busy dout dout busy busy dout 2 mosi/csi_b mosi csi_b csi_b 2 d7 d7 d7 2 d6 d6 d6 2 d5 d5 d5 2 d4 d4 d4 2 functional description 58 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r d3 d3 d3 2 d2 d2 d2 2 d1 d1 d1 2 d0/din din din d0 d0 din 2 rdwr_b rdwr_b rdwr_b 2 a23 a23 2 a22 a22 2 a21 a21 2 a20 a20 2 a19/vs2 vs2 a19 2 a18/vs1 vs1 a18 2 a17/vs0 vs0 a17 2 a16 a16 1 a15 a15 1 a14 a14 1 a13 a13 1 a12 a12 1 a11 a11 1 a10 a10 1 a9 a9 1 a8 a8 1 a7 a7 1 a6 a6 1 a5 a5 1 a4 a4 1 a3 a3 1 a2 a2 1 a1 a1 1 a0 a0 1 ldc0 ldc0 ldc0 1 ldc1 ldc1 ldc1 1 ldc2 ldc2 ldc2 1 hdc hdc hdc 1 table 40: pin behavior during configuration (continued) pin name master serial spi (serial flash) bpi (parallel nor flash) jtag slave parallel slave serial supply/ i/o bank functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 59 advance product specification r ta b l e 4 1 shows the default i/o standard setting for the vari- ous configuration pins during the configuration process. the configuration interface is designed primarily for 2.5v opera- tion when the vcco_2 (and vcco_1 in bpi mode) con- nects to 2.5v. the configuration pins also operate at other voltages by set- ting vcco_2 (and vcco_1 in bpi mode) to either 3.3v or 1.8v. the change on the vcco supply also changes the i/o drive characteristics. for example, with vcco = 3.3v, the output current when driving high, i oh , increases to approx- imately 12 to 16 ma, while the current when driving low, i ol , remains 8 ma. at vcco = 1.8v, the output current when driving high, i oh , decreases slightly to approximately 6 to 8 ma. again, the current when driving low, i ol , remains 8 ma. master serial mode in master serial mode (m[2:0] = <0:0:0>), the spartan-3e fpga configures itself from an attached xilinx platform flash prom, as illustrated in figure 48 . the fpga sup- plies the cclk output clock from its internal oscillator to the attached platform flash prom. in response, the platform flash prom supplies bit-serial data to the fpga?s din input and the fpga accepts this data on each rising cclk edge. table 41: default i/o standard setting during configuration (vcco_2 = 2.5v) pin(s) i/o standard output drive slew rate all, including cclk lvcmos25 8 ma slow figure 48: master serial mode using platform flash prom tdi tdo tms tck vccint vccaux +2.5v init_b vcco_2 cclk din prog_b done gnd +1.2v d0 cf vccint clk hswap vcco_0 p vcco_0 spartan-3e +2.5v jtag prog_b recommend open-drain driver tdi tms tck tdo xcfxxs = +3.3v xcfxxp = +1.8v ce m2 m1 ? ? m0 serial master mode ? dout oe/reset v v gnd tdi tms tck tdo vccj +2.5v vcco v ceo platform flash xcfxx 330 +2.5v 4.7k 4.7k ds312-2_44_021405 functional description 60 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the mode select pins, m[2:0], must all be low when sam- pled, when the fpga?s init_b output goes high. after con- figuration, when the fpga?s done output goes high, the mode select pins are available as full-featured user-i/o pins. similarly, the fpga?s hswap pin must be low to enable pull-up resistors on all user-i/o pins during configu- ration or high to disable the pull-up resistors. the hswap control must remain at a constant logic level throughout fpga configuration. after configuration, when the fpga?s done output goes high, the hswap pin is available as full-featured user-i/o pin and is powered by the vcco_0 supply. the fpga's dout pin is used in daisy-chain applications, described later. in a single-fpga application, the fpga?s dout pin is not used but is actively driving during the con- figuration process. p table 42: serial master mode connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-ups during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. m2 = 0, m1 = 0, m0 = 0. sampled when init_b goes high. user i/o din input serial data input . receives serial data from prom?s d0 output. user i/o cclk output configuration clock . generated by fpga internal oscillator. frequency controlled by configrate bitstream generator option. if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. drives prom?s clk clock input. user i/o dout output serial data output . actively drives. not used in single-fpga designs. in a daisy-chain configuration, this pin connects to din input of the next fpga in the chain. user i/o init_b open-drain bidirectional i/o initialization indicator . active low. goes low at start of configuration during initialization memory clearing process. released at end of memory clearing, when mode select pins are sampled. requires external 4.7 k ? pull-up resistor to vcco_2. connects to prom?s oe/reset input. fpga clears prom?s address counter at start of configuration, enables outputs during configuration. prom also holds fpga in initialization state until prom reaches power-on reset (por) state. if crc error detected during configuration, fpga drives init_b low. user i/o p functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 61 advance product specification r voltage compatibility the prom?s v ccint supply must be either 3.3v for the serial xcfxxs platform flash proms or 1.8v for the serial/parallel xcfxxp proms. the fpga?s vcco_2 supply input and the platform flash prom?s v cco supply input must be the same volt- age, ideally +2.5v. both devices also support 1.8v and 3.3v interfaces but the fpga?s prog_b and done pins require special attention as they are powered by the fpga?s vccaux supply, nominally 2.5v. see application note xapp453 : "the 3.3v configuration of spartan-3 fpgas" for additional information. supported platform flash proms ta b l e 4 3 shows the smallest available platform flash prom to program a single spartan-3e fpga. a multi- ple-fpga daisy-chain application requires a platform flash prom large enough to contain the sum of the various fpga file sizes. the xc3s1600e requires an 8 mbit prom. there are two possible solutions. either use a single 8 mbit xcf08p par- allel/serial prom or cascade two 4 mbit xcf04s serial proms. the two xcf04s proms use a 3.3v v ccint sup- ply while the xcf08p requires a 1.8v v ccint supply. if the board does not already have a 1.8v supply available, the two cascaded xcf04s prom solution is recommended. cclk frequency in master serial mode, the fpga?s internal oscillator gener- ates the configuration clock frequency. the fpga provides this clock on its cclk output pin, driving the prom?s clk input pin. the fpga starts configuration at its lowest fre- quency and increases its frequency for the remainder of the configuration process if so specified in the configuration bit- stream. the maximum frequency is specified using the configrate bitstream generator option. ta b l e 4 4 shows the maximum configrate settings, approximately equal to mhz, for various platform flash devices and i/o voltages. for the serial xcfxxs proms, the maximum frequency also depends on the interface voltage. done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully completes configuration. requires external 330 ? pull-up resistor to 2.5v. connects to prom?s chip-enable (ce) input. enables prom during configuration. disables prom after configuration. pulled high via external pull-up. when high, indicates that the fpga successfully configured. prog_b input program fpga . active low. when asserted low for 300 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. requires external 4.7 k ? pull-up resistor to 2.5v. if driving externally, use an open-drain or open-collector driver. must be high during configuration to allow configuration to start. connects to prom?s cf pin, allowing jtag prom programming algorithm to reprogram the fpga. drive prog_b low and release to reprogram fpga. table 42: serial master mode connections (continued) pin name fpga direction description during configuration after configuration table 43: number of bits to program a spartan-3e fpga and smallest platform flash prom device number of configuration bits smallest available platform flash XC3S100E 581,344 xcf01s xc3s250e 1,352,192 xcf02s xc3s500e 2,267,136 xcf04s xc3s1200e 3,832,320 xcf04s xc3s1600e 5,957,760 xcf08p or 2 x xcf04s v table 44: maximum configrate settings for platform flash platform flash part number i/o voltage (vcco_2, vcco) maximum configrate setting xcf01s xcf02s xcf04s 3.3v or 2.5v 25 1.8v 12 xcf08p xcf16p xcf32p 3.3v, 2.5v, or 1.8v 25 functional description 62 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r daisy-chaining if the application requires multiple fpgas with different con- figurations, then configure the fpgas using a daisy chain, as shown in figure 49 . use master serial mode (m[2:0] = <0:0:0>) for the fpga connected to the platform flash prom and slave serial mode (m[2:0] = <1:1:1>) for all other fpgas in the daisy-chain. after the master fpga?the fpga on the left in the diagram?finishes load- ing its configuration data from the platform flash, the mas- ter device supplies data using its dout output pin to the next device in the daisy-chain, on the falling cclk edge. jtag interface both the spartan-3e fpga and the platform flash prom have a four-wire ieee 1149.1/1532 jtag port. both devices share the tck clock input and the tms mode select input. the devices may connect in either order on the jtag chain with the tdo output of one device feeding the tdi input of the following device in the chain. the tdo output of the last device in the jtag chain drives the jtag connector. the jtag interface on spartan-3e fpgas is powered by the 2.5v vccaux supply. consequently, the prom?s v ccj supply input must also be 2.5v. to create a 3.3v jtag inter- face, please refer to application note xapp453 : "the 3.3v configuration of spartan-3 fpgas" for additional informa- tion. in-system programming support both the fpga and the platform flash prom are in-system programmable via the jtag chain. download support is provided by the xilinx impact programming software and the associated xilinx parallel cable iv , multipro , or plat- form cable usb programming cables. storing additional user data in platform flash after configuration, the fpga application can continue to use the master serial interface pins to communicate with the platform flash prom. if desired, use a larger platform flash prom to hold additional non-volatile application data, such as microblaze processor code, or other user data such as serial numbers and ethernet mac ids. the fpga first configures from platform flash prom. then using fpga logic after configuration, the fpga copies microblaze code from platform flash into external ddr sdram for code execution. see xapp694 : "reading user data from configuration proms" and xapp482 : "microblaze platform flash/prom boot loader and user data storage" for specific details on how to implement such an interface. spi serial flash mode in spi serial flash mode ( m[2:0] = <0:0:0> ), the spartan-3e fpga configures itself from an attached industry-standard spi serial flash prom, as illustrated in figure 50 and figure 52 . the fpga supplies the cclk output clock from its internal oscillator to the clock input of the attached spi flash prom. figure 49: daisy-chaining from master serial mode +2.5v tdi tdo tms tck vccint vccaux +2.5v init_b vcco_2 cclk din prog_b done gnd +1.2v d0 cf vccint clk hswap vcco_0 p tdi tdo tms tck vccint vccaux din dout vcco_2 init_b prog_b done gnd +1.2v m2 m1 ? ? m0 hswap vcco_0 p +2.5v ? vcco_0 slave serial mode spartan-3e fpga spartan-3e fpga +2.5v jtag cclk init_b done prog_b tck tms prog_b recommend open-drain driver vcco_0 tdi tms tck tdo xcfxxs = +3.3v xcfxxp = +1.8v ce m2 m1 ? ? m0 serial master mode ? dout dout cclk oe/reset v v gnd tdi tms tck tdo vccj +2.5v vcco v ceo platform flash xcfxx 4.7k 4.7k 330 v ds312-2_45_021405 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 63 advance product specification r although spi is a standard four-wire interface, various available spi flash proms use different command proto- cols. the fpga?s variant select pins, vs[2:0], define how the fpga communicates with the spi flash, including which spi flash command the fpga issues to start the read operation and the number of dummy bytes inserted before the fpga expects to receive valid data from the spi flash. ta bl e 4 5 shows the available spi flash proms expected to operate with spartan-3e fpgas. other com- patible devices might work but have not been tested for suit- ability with spartan-3e fpgas. all other vs[2:0] values are reserved for future use. figure 50 shows the general connection diagram for those spi flash proms that support the 0x03 read command or the 0x0b fast read commands. figure 51 shows the connection diagram for atmel dataflash serial proms, which also use an spi-based pro- tocol. figure 54 demonstrates how to configure multiple fpgas with different configurations, all stored in a single spi flash. the diagram uses standard spi flash memories but the same general technique applies for atmel dataflash. figure 50: spi flash prom interface for proms supporting read (0x03) and fast_read (0x0b) ds312-2_46_021405 tdi tdo tms tck vccint vccaux +2.5v cso_b vcco_2 init_b din mosi prog_b done gnd +1.2v data_in select vcc data_out clock gnd hswap vcco_0 p cclk vcco_0 spartan-3e fpga +2.5v jtag spi serial flash prog_b recommend open-drain driver tdi tms tck tdo +3.3v +3.3v hold ? m2 m1 ? ? m0 spi mode ? vs2 vs1 ? vs0 variant select ? s dout wr_protect w p i 4.7k +3.3v 4.7k +2.5v 4.7k 330 s functional description 64 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r figure 51: atmel spi-based dataflash configuration interface tdi tdo tms tck vccint vccaux +2.5v cso_b vcco_2 init_b din mosi prog_b done gnd si cs vcc so sck gnd hswap vcco_0 p cclk vcco_0 spartan-3e fpga +2.5v jtag atmel at45db dataflash prog_b recommend open-drain driver tdi tms tck tdo +3.3v +3.3v reset ?1? m2 m1 ?0? ?0? m0 spi mode ?1? vs2 vs1 ?1? vs0 variant select ?0? dout wp w p i 4.7k +3.3v 4.7 k ? +2.5v 4.7k ? 330 ? ?1? rdy/busy +1.2v power-on monitor +3.3v power-on monitor +3.3v or power-on monitor is only required if +3.3v (vcco_2) supply is last supply in power-on sequence, after vccint and vccaux. must delay fpga configuration for > 20 ms after spi dataflash reaches its minimum vcc. force fpga init_b input or prog_ b input low with an open-drain or open- collector driver. init_b prog_b ds312-2_50a_022305 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 65 advance product specification r ta b l e 4 6 shows the connections between the spi flash prom and the fpga?s spi configuration interface. each spi flash prom vendor uses slightly different signal nam- ing. the spi flash prom?s write protect and hold controls are not used by the fpga during configuration. however, the hold pin must be high during the configuration pro- cess. the prom?s write protect input must be high in order to write or program the flash memory. table 45: variant select codes for spi serial flash proms vs2 vs1 vs0 spi read command dummy bytes spi serial flash vendor spi flash family 1 1 1 fast read (0x0b) (see figure 50 ) 1 stmicroelectronics (st) m25pxx nexflash nx25pxx silicon storage technology (sst) sst25lfxxxa sst25vfxxxa programmable microelectronics corp. (pmc) pm25lvxxx 1 0 1 read (0x03) (see figure 50 ) 0 stmicroelectronics (st) m25pxx nexflash nx25pxx silicon storage technology (sst) sst25lfxxxa sst25vfxxxa sst25vfxxx programmable microelectronics corp. (pmc) pm25lvxxx 1 1 0 read array (0xe8) (see figure 51 ) 3 atmel corporation at45db dataflash others reserved w table 46: spi flash prom connections and pin naming spi flash pin fpga connection stmicro nexflash silicon storage technology atmel dataflash data_in mosi d di si si data_out din q do so so select cso_b s cs ce# cs clock cclk c clk sck sck wr_protect not required for fpga configuration. must be high to program spi flash. optional connection to fpga user i/o after configuration. w wp wp# wp hold (see figure 50 ) not required for fpga configuration but must be high during configuration. optional connection to fpga user i/o after configuration. not applicable to atmel dataflash. hold hold hold# n/a w functional description 66 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the mode select pins, m[2:0], and the variant select pins, vs[2:0] are sampled when the fpga?s init_b output goes high and must be at defined logic levels during this time. after configuration, when the fpga?s done output goes high, these pins are all available as full-featured user-i/o pins. similarly, the fpga?s hswap pin must be low to enable pull-up resistors on all user-i/o pins or high to dis- able the pull-up resistors. the hswap control must remain at a constant logic level throughout fpga configuration. after configuration, when the fpga?s done output goes high, the hswap pin is available as full-featured user-i/o pin and is powered by the vcco_0 supply. in a single-fpga application, the fpga?s dout pin is not used but is actively driving during the configuration process. reset (see figure 51 ) only applicable to atmel dataflash. not required for fpga configuration but must be high during configuration. optional connection to fpga user i/o after configuration. do not connect to fpga?s prog_b as this will prevent direct programming of the dataflash. n/a n/a n/a reset rdy/busy (see figure 51 ) only applicable to atmel dataflash and only available on certain packages. not required for fpga configuration. output from dataflash prom. optional connection to fpga user i/o after configuration. n/a n/a n/a rdy/busy table 46: spi flash prom connections and pin naming (continued) spi flash pin fpga connection stmicro nexflash silicon storage technology atmel dataflash p table 47: serial peripheral interface (spi) connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-ups during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. m2 = 0, m1 = 0, m0 = 1. sampled when init_b goes high. user i/o vs[2:0] input variant select . instructs the fpga how to communicate with the attached spi flash prom. must be at the logic levels shown in ta b l e 4 5 . sampled when init_b goes high. user i/o mosi output serial data output . fpga sends spi flash memory read commands and starting address to the prom?s serial data input. user i/o din input serial data input . fpga receives serial data from prom?s serial data output. user i/o p s functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 67 advance product specification r voltage compatibility available spi flash proms use a single 3.3v supply volt- age. all of the fpga?s spi flash interface signals are within i/o bank 2. consequently, the fpga?s vcco_2 supply volt- age must also be 3.3v to match the spi flash prom. cso_b output chip select output . active low. connects to the spi flash prom?s chip-select input. if hswap = 1, connect this signal to a 4.7 k ? pull-up resistor to 3.3v. drive cso_b high after configuration to disable the spi flash and reclaim the mosi, din, and cclk pins. optionally, re-use this pin and mosi, din, and cclk to continue communicating with spi flash. cclk output configuration clock . generated by fpga internal oscillator. frequency controlled by configrate bitstream generator option. if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. drives prom?s clock input. user i/o dout output serial data output . actively drives. not used in single-fpga designs. in a daisy-chain configuration, this pin connects to din input of the next fpga in the chain. user i/o init_b open-drain bidirectional i/o initialization indicator . active low. goes low at start of configuration during initialization memory clearing process. released at end of memory clearing, when mode select pins are sampled. in daisy-chain applications, this signal requires an external 4.7 k ? pull-up resistor to vcco_2. active during configuration. if spi flash prom requires > 2 ms to awake after powering on, hold init_b low until prom is ready. if crc error detected during configuration, fpga drives init_b low. user i/o done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully completes configuration. requires external 330 ? pull-up resistor to 2.5v. low indicates that the fpga is not yet configured. pulled high via external pull-up. when high, indicates that the fpga successfully configured. prog_b input program fpga . active low. when asserted low for 300 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. requires external 4.7 k ? pull-up resistor to 2.5v. if driving externally, use an open-drain or open-collector driver. must be high to allow configuration to start. drive prog_b low and release to reprogram fpga. hold prog_b to force fpga i/o pins into hi-z, allowing direct programming access to spi flash prom pins. table 47: serial peripheral interface (spi) connections (continued) pin name fpga direction description during configuration after configuration functional description 68 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r power-on precautions if 3.3v supply is last in sequence spartan-3e fpgas have a built-in power-on reset (por) circuit, as shown in figure 63 . the fpga waits for its three power supplies ? vccint, vccaux, and vcco to i/o bank 2 (vcco_2) ? to reach their respective power-on thresholds before beginning the configuration process. the spi flash prom is powered by the same voltage sup- ply feeding the fpga's vcco_2 voltage input, typically 3.3v. spi flash proms specify that they cannot be accessed until their vcc supply reaches its minimum data sheet voltage, followed by an additional delay. for some devices, this additional delay is as little as 10 s as shown in ta b l e 4 8 . for other vendors, it is as much as 20 ms. in many systems, the 3.3v supply feeding the fpga's vcco_2 input is valid before the fpga's other vccint and vccaux supplies, and consequently, there is no issue. however, if the 3.3v supply feeding the fpga's vcco_2 supply is last in the sequence, a potential race occurs between the fpga and the spi flash prom, as shown in figure 52 . if the fpga's vccint and vccaux supplies are already valid, then the fpga waits for vcco_2 to reach its mini- mum threshold voltage before starting configuration. this threshold voltage is labeled as v cco2t in module 3 and ranges from approximately 0.4v to 1.0v, substantially lower than the spi flash prom's minimum voltage. once all three fpga supplies reach their respective power on reset (por) thresholds, the fpga starts the configuration process and begins initializing its internal configuration memory. initialization requires approximately 1 ms (t por , minimum in module 3 ), after which the fpga deasserts init_b, selects the spi flash prom, and starts sending the appropriate read command. the spi flash prom must be ready for read operations at this time. if the 3.3v supply is last in the sequence and does not ramp fast enough, or if the spi flash prom cannot be ready when required by the fpga, delay the fpga configuration process by holding either the fpga's prog_b input or init_b input low, as highlighted in figure 51 . release the fpga when the spi flash prom is ready. for example, a simple r-c delay circuit attached to the init_b pin forces the fpga to wait for a preselected amount of time. alter- nately, a power good signal from the 3.3v supply or a sys- tem reset signal accomplishes the same purpose. use an open-drain or open-collector output when driving prog_b or init_b. table 48: example minimum power-on to select times for various spi flash proms vendor spi flash prom part number data sheet minimum time from vcc, min. to select = low symbol value units stmicroelectronics m25pxx t vsl 10 s nexflash nx25xx t vsl 10 s silicon storage technology sst25lfxx t pu-read 10 s programmable microelectronics corporation pm25lvxxx t vcs 50 s atmel corporation at45dbxx 20 ms figure 52: spi flash prom/fpga power-on timing if 3.3v supply is last in power-on sequence fpga vcco_2 minimum power on reset voltage (v cco2t ) spi flash prom minimum voltage spi flash available for read operations spi flash (t vsl ) spi flash cannot be selected fpga initializes configuration memory 3.3v supply fpga accesses spi flash prom time spi flash prom must be ready for fpga access otherwise delay fpga configuration ds312-2_50b_022405 (t por ) (vccint, vccaux already valid) prom cs delay functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 69 advance product specification r spi flash prom density requirements ta b l e 4 9 shows the smallest usable spi flash prom to program a single spartan-3e fpga. commercially avail- able spi flash proms range in density from 1 mbit to 128 mbits. a multiple-fpga daisy-chained application requires a spi flash prom large enough to contain the sum of the fpga file sizes. an application can also use a larger-den- sity spi flash prom to hold additional data beyond just fpga configuration data. for example, the spi flash prom can also store application code for a microblaze? risc processor core integrated in the spartan-3e fpga. see using the spi flash interface after configuration . cclk frequency in spi flash mode, the fpga?s internal oscillator generates the configuration clock frequency. the fpga provides this clock on its cclk output pin, driving the prom?s clock input pin. the fpga starts configuration at its lowest frequency and increases its frequency for the remainder of the config- uration process if so specified in the configuration bitstream. the maximum frequency is specified using the configrate bitstream generator option. the maximum frequency sup- ported by the fpga configuration logic depends on the tim- ing for the spi flash device. without examining the timing for a specific spi flash prom, use configrate =12, which is approximately 12 mhz. spi flash proms that sup- port the fast read command support higher data rates. some such proms support up to configrate = 25 and beyond but require careful data sheet analysis. using the spi flash interface after configuration after the fpga successfully completes configuration, all of the pins connected to the spi flash prom are available as user-i/o pins. if not using the spi flash prom after configuration, drive cso_b high to disable the prom. the mosi, din, and cclk pins are then available to the fpga application. because all the interface pins are user i/o after configura- tion, the fpga application can continue to use the spi flash interface pins to communicate with the spi flash prom, as shown in figure 53 . spi flash proms offer ran- dom-accessible, byte-addressable, read/write, non-volatile storage to the fpga application. spi flash proms are available in densities ranging from 1 mbit up to 128 mbits. however, a single spartan-3e fpga requires less than 6 mbits. if desired, use a larger spi flash prom to contain additional non-volatile application data, such as microblaze processor code, or other user data such as serial numbers and ethernet mac ids. in the example shown in figure 53 , the fpga configures from spi flash prom. then using fpga logic after configuration, the fpga copies microblaze code from spi flash into external ddr sdram for code execution. similarly, the fpga appli- cation can store non-volatile application data within the spi flash prom. the fpga configuration data is stored starting at location 0. store any additional data beginning in the next available spi flash prom sector or page. do not mix configuration data and user data in the same sector or page. table 49: number of bits to program a spartan-3e fpga and smallest spi flash prom device number of configuration bits smallest usable spi flash prom XC3S100E 581,344 1 mbit xc3s250e 1,352,192 2 mbit xc3s500e 2,267,136 4 mbit xc3s1200e 3,832,320 4 mbit xc3s1600e 5,957,760 8 mbit functional description 70 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r similarly, the spi bus can be expanded to additional spi peripherals. because spi is a common industry-standard interface, there are a variety of spi-based peripherals avail- able, including analog-to-digital (a/d) converters, digi- tal-to-analog (d/a) converters, can controllers, and temperature sensors. the mosi, din, and cclk pins are common to all spi peripherals. connect the select input on each additional spi peripheral to one of the fpga user i/o pins. if hswap = 0 during configuration, the fpga holds the select line high. if hswap = 1, connect the select line to +3.3v via an external 4.7 k ? pull-up resistor to avoid spurious read or write oper- ations. after configuration, drive the select line low to select the desired spi peripheral. refer to the individual spi peripheral data sheet for specific interface and communica- tion protocol requirements. daisy-chaining if the application requires multiple fpgas with different con- figurations, then configure the fpgas using a daisy chain, as shown in figure 54 . use spi flash mode (m[2:0] = <0:0:1>) for the fpga connected to the platform flash prom and slave serial mode (m[2:0] = <1:1:1>) for all other fpgas in the daisy-chain. after the master fpga?the fpga on the left in the diagram?finishes load- ing its configuration data from the spi flash prom, the master device uses its dout output pin to supply data to the next device in the daisy-chain, on the falling cclk edge. figure 53: using the spi flash interface after configuration mosi din cclk cso_b data_in data_out clock select data_in data_out clock select spi serial flash prom fpga configuration microblaze code user data 0 fffff spi peripherals ? a/d converter ? d/a converter ? can controller ? temperature sensor ? displays ? temperature sensor ? microcontroller ? assp fpga-based spi master user-i/o 4.7k ? +3.3v to other spi slave peripherals spartan-3e fpga ddr sdram ds312-2_47_022205 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 71 advance product specification r in-system programming support in a production application, the spi flash prom is usu- ally pre-programmed before it is mounted on the printed cir- cuit board. in-system programming support is available from some third-party prom programmers using a socket adapter with attached wires. to gain access to the spi flash signals, drive the fpga?s prog_b input low with an open-drain driver. this action places all fpga i/o pins, including those attached to the spi flash, in high-imped- ance (hi-z). if the hswap input is high, the i/os have pull-up resistors to the v cco input on their respective i/o bank. the external programming hardware then has direct access to the spi flash pins. the programming access points are highlighted in the gray box in figure 50 , figure 51 , and figure 54 . byte-wide peripheral interface (bpi) parallel flash mode in byte-wide peripheral interface (bpi) mode (m[2:0] = <0:1:0> or <0:1:1>), a spartan-3e fpga config- ures itself from an industry-standard parallel nor flash prom, as illustrated in figure 55 . the fpga generates up to a 24-bit address lines to access an attached parallel flash. only 20 address lines are generated for spartan-3e fpgas in the tq144 package. the bpi mode is not avail- able for spartan-3e fpgas in the vq100 package. the interface is designed for standard parallel nor flash proms and supports both byte-wide (x8) and byte-wide/halfword (x8/x16) proms. the interface does not support halfword-only (x16) proms. the interface works equally wells with other memories that use a similar inter- face such as sram, nvram, eeprom, eprom, or masked rom but is primarily designed for flash memory. there is another type of flash memory called nand flash, which is commonly used in memory cards for digital cam- eras, etc. spartan-3e fpgas do not configure directly from nand flash memories. the fpga?s internal oscillator controls the interface timing and the fpga supplies the clock on the cclk output pin. however, the cclk signal is not used in single fpga appli- cations. similarly, the fpga drives three pins low during configuration (ldc[2:0]) and one pin high during configura- tion (hdc) to the prom?s control inputs. figure 54: daisy-chaining from spi flash mode +2.5v tdi tdo tms tck vccint vccaux +2.5v cso_b vcco_2 init_b din mosi prog_b done gnd +1.2v data _ i n select vcc data _ o u t clock gnd hswap vcco_0 p cclk tdi tdo tms tck vccint vccaux din dout vcco_2 init_b prog_b done gnd +1.2v m2 m1 ? ? m0 hswap vcco_0 p +3.3v +2.5v ? vcco_0 4.7k slave serial mode +2.5v jtag cclk init_b done prog_b tck tms spi serial flash prog_b recommend open-drain driver vcco_0 tdi tms tck tdo +3.3v +3.3v hold ? m2 m1 ? ? m0 spi mode ? vs2 vs1 ? vs0 variant select ? s dout spartan-3e fpga spartan-3e fpga dout cclk wr_protect w +3.3v p 4.7k 330 i 4.7k ds312-2_48_021405 i functional description 72 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r during configuration, the value of the m0 mode pin determines how the fpga generates addresses, as shown ta b l e 5 0 . when m0 = 0, the fpga generates addresses starting at 0 and increments the address on every falling cclk edge. conversely, when m0 = 1, the fpga gener- ates addresses starting at 0xff_ffff (all ones) and decre- ments the address on every falling cclk edge. this addressing flexibility allows the fpga to share the par- allel flash prom with an external or embedded processor. depending on the specific processor architecture, the pro- cessor boots either from the top or bottom of memory. the fpga is flexible and boots from the opposite end of mem- ory from the processor. only the processor or the fpga can boot at any given time. the fpga can configure first, hold- ing the processor in reset or the processor can boot first, asserting the fpga?s prog_b pin. the mode select pins, m[2:0], are sampled when the fpga?s init_b output goes high and must be at defined logic levels during this time. after configuration, when the fpga?s done output goes high, the mode pins are avail- able as full-featured user-i/o pins. similarly, the fpga?s hswap pin must be low to enable pull-up resistors on all user-i/o pins or high to dis- able the pull-up resistors. the hswap control must remain at a constant logic level throughout fpga configuration. after configuration, when the fpga?s done output goes figure 55: byte-wide peripheral interface (bpi) mode configured from parallel nor flash proms tdi tdo tms tck vccint vccaux +2.5v hdc cclk cso_b vcco_1 init_b csi_b d[7:0] ldc1 ldc0 ? a[16:0] prog_b done gnd vcco_2 +1.2v dq[7:0] a[n:0] ce# we# vcco oe# byte# dq[15:7] gnd m2 m1 ? ? m0 hswap vcco_0 a a[23:17] p ldc2 vcco_0 v v v bpi mode +2.5v jtag x8 or x8/x16 flash prom prog_b recommend open-drain driver tdi tms tck tdo rdwr_b ? spartan-3e fpga busy i not available in vq100 package v 4.7k ? +2.5v 4.7k ? 3 3 0 ? ds312-2_49_022305 d table 50: bpi addressing control m2 m1 m0 start address addressing 0 1 0 0 incrementing 1 0xff_ffff decrementing a p functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 73 advance product specification r high, the hswap pin is available as full-featured user-i/o pin and is powered by the vcco_0 supply. the rdwr_b and csi_b must be low throughout the con- figuration process. after configuration, these pins also become user i/o. in a single-fpga application, the fpga?s cso_b and cclk pins are not used but are actively driving during the configuration process. the busy pin is not used but also actively drives during configuration and is available as a user i/o after configuration. after configuration, all of the interface pins except done and prog_b are available as user i/os. furthermore, the bidirectional selectmap configuration peripheral interface (see slave parallel mode ) is available after configuration. to continue using selectmap mode, set the persist bit- stream generator option to yes . an external host can then read and verify configuration data. table 51: byte-wide peripheral interface (bpi) connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-ups during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. m2 = 0, m1 = 1. set m0 = 0 to start at address 0, increment addresses. set m0 = 1 to start at address 0xffffff and decrement addresses. sampled when init_b goes high. user i/o csi_b input chip select input . active low. must be low throughout configuration. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. rdwr_b input read/write control . active low write enable. read functionality typically only used after configuration, if bitstream option persist=yes . must be low throughout configuration. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. ldc0 output prom chip enable connect to prom chip-select input (ce#). fpga drives this signal low throughout configuration. user i/o ldc1 output prom output enable connect to prom output-enable input (oe#). fpga drives this signal low throughout configuration. user i/o hdc output prom write enable connect to prom write-enable input (we#). fpga drives this signal high throughout configuration. user i/o ldc2 output prom byte mode this signal is not used for x8 proms. for proms with a x8/x16 data width control, connect to prom byte-mode input (byte#). see precautions using x8/x16 flash proms . fpga drives this signal low throughout configuration. user i/o. drive this pin high after configuration to use a x8/x16 prom in x16 mode. p a d functional description 74 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r a[23:0] output address connect to prom address inputs. high order address lines may not be available in all packages and not all may be required. number of address lines required depends on the size of the attached flash prom. fpga address generation controlled by m0 mode pin. addresses presented on falling cclk edge. only 20 address lines are available in tq144 package. user i/o d[7:0] input data input fpga receives byte-wide data on these pins in response the address presented on a[23:0]. data captured by fpga user i/o if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. cso_b output chip select output . active low. not used in single fpga applications. in a daisy-chain configuration, this pin connects to the csi_b pin of the next fpga in the chain. actively drives. user i/o busy output busy indicator . typically only used after configuration, if bitstream option persist=yes . not used during configuration but actively drives. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. cclk output configuration clock . generated by fpga internal oscillator. frequency controlled by configrate bitstream generator option. if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. not used in single fpga applications but actively drives. in a daisy-chain configuration, drives the cclk inputs of all other fpgas in the daisy-chain. user i/o if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. init_b open-drain bidirectional i/o initialization indicator . active low. goes low at start of configuration during initialization memory clearing process. released at end of memory clearing, when mode select pins are sampled. in daisy-chain applications, this signal requires an external 4.7 k ? pull-up resistor to vcco_2. active during configuration. if crc error detected during configuration, fpga drives init_b low. user i/o table 51: byte-wide peripheral interface (bpi) connections (continued) pin name fpga direction description during configuration after configuration functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 75 advance product specification r voltage compatibility the fpga?s parallel flash interface signals are within i/o banks 1 and 2. the majority of parallel flash proms use a single 3.3v supply voltage. consequently, in most cases, the fpga?s vcco_1 and vcco_2 supply voltages must also be 3.3v to match the parallel flash prom. there are some 1.8v parallel flash proms available and the fpga interfaces with these devices if the vcco_1 and vcco_2 supplies are also 1.8v. supported parallel nor flash prom densities ta b l e 5 2 indicates the smallest usable parallel flash prom to program a single spartan-3e fpga. parallel flash den- sity is specified in bits but addressed as bytes. the fpga presents up to 24 address lines during configuration but not all are required for single fpga applications. ta bl e 5 2 shows the minimum required number of address lines between the fpga and parallel flash prom. the actual number of address line required depends on the density of the attached parallel flash prom. a multiple-fpga daisy-chained application requires a par- allel flash prom large enough to contain the sum of the fpga file sizes. an application may also use a larger-den- sity parallel flash prom to hold additional data beyond just fpga configuration data. for example, the parallel flash prom could also contain the application code for a micro- blaze risc processor core implemented within the spar- tan-3e fpga. after configuration, the microblaze processor could execute directly from external flash or could copy the code to other, faster system memory before executing the code. cclk frequency in bpi mode, the fpga?s internal oscillator generates the configuration clock frequency that controls all the interface timing. the fpga starts configuration at its lowest fre- quency and increases its frequency for the remainder of the configuration process if so specified in the configuration bit- stream. the maximum frequency is specified using the configrate bitstream generator option. ta b l e 5 3 shows the maximum configrate settings, approximately equal to mhz, for various prom read access times. despite using slower configrate settings, bpi mode is equally fast as the other configuration modes. in bpi mode, data is accessed done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully completes configuration. requires external 330 ? pull-up resistor to 2.5v. low indicates that the fpga is not yet configured. pulled high via external pull-up. when high, indicates that the fpga successfully configured. prog_b input program fpga . active low. when asserted low for 300 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. requires external 4.7 k ? pull-up resistor to 2.5v. if driving externally, use an open-drain or open-collector driver. must be high to allow configuration to start. drive prog_b low and release to reprogram fpga. hold prog_b to force fpga i/o pins into hi-z, allowing direct programming access to flash prom pins. table 51: byte-wide peripheral interface (bpi) connections (continued) pin name fpga direction description during configuration after configuration v table 52: number of bits to program a spartan-3e fpga and smallest parallel flash prom device uncompressed file sizes (bits) smallest usable parallel flash prom minimum required address lines XC3S100E 581,344 1 mbit a[16:0] xc3s250e 1,352,192 2 mbit a[17:0] xc3s500e 2,267,136 4 mbit a[18:0] xc3s1200e 3,832,320 4 mbit a[18:0] xc3s1600e 5,957,760 8 mbit a[19:0] functional description 76 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r at the configrate frequency and internally serialized with an 8x clock frequency. using the bpi interface after configuration after the fpga successfully completes configuration, all of the pins connected to the parallel flash prom are available as user i/os. if not using the parallel flash prom after configuration, drive ldc0 high to disable the prom?s chip-select input. the remainder of the bpi pins then become available to the fpga application, including all 24 address lines, the eight data lines, and the ldc2, ldc1, and hdc control pins. because all the interface pins are user i/os after configura- tion, the fpga application can continue to use the interface pins to communicate with the parallel flash prom. parallel flash proms are available in densities ranging from 1 mbit up to 128 mbits and beyond. however, a single spartan-3e fpga requires less than 6 mbits for configuration. if desired, use a larger parallel flash prom to contain addi- tional non-volatile application data, such as microblaze pro- cessor code, or other user data such as serial numbers, ethernet mac ids, etc. in such an example, the fpga con- figures from parallel flash prom. then using fpga logic after configuration, a microblaze processor embedded within the fpga can either execute code directly from par- allel flash prom or copy the code to external ddr sdram and execute from ddr sdram. similarly, the fpga application can store non-volatile application data within the parallel flash prom. the fpga configuration data is stored starting at either at location 0 or the top of memory (addresses all ones) or at both locations for multiboot mode. store any additional data beginning in other available parallel flash prom sectors. do not mix configuration data and user data in the same sector. similarly, the parallel flash prom interface can be expanded to additional parallel peripherals. the address, data, and ldc1 (oe#) and hdc (we#) con- trol signals are common to all parallel peripherals. connect the chip-select input on each additional peripheral to one of the fpga user i/o pins. if hswap = 0 during configuration, the fpga holds the chip-select line high via an internal pull-up resistor. if hswap = 1, connect the select line to +3.3v via an external 4.7 k ? pull-up resistor to avoid spuri- ous read or write operations. after configuration, drive the select line low to select the desired peripheral. refer to the individual peripheral data sheet for specific interface and communication protocol requirements. the fpga optionally supports a 16-bit peripheral interface by driving the ldc2 (byte#) control pin high after configu- ration. see precautions using x8/x16 flash proms for additional information. the fpga provides up to 24 address lines during configu- ration, addressing up to 128 mbits (16 mbytes). if using a larger parallel prom, connect the upper address lines to fpga user i/o. during configuration, the upper address lines will be pulled high if hswap = 0. otherwise, use external pull-up or pull-down resistors on these address lines to define their values during configuration. precautions using x8/x16 flash proms most low- to mid-density proms are byte-wide (x8) only. many higher-density flash proms support both byte-wide (x8) and halfword-wide (x16) data paths and include a mode input called byte# that switches between x8 or x16. during configuration, spartan-3e fpgas only support byte-wide data. however, after configuration, the fpga supports either x8 or x16 modes. in x16 mode, up to eight additional user i/o pins are required for the upper data bits, d[15:8]. connecting a spartan-3e fpga to a x8/x16 flash prom is simple, but does require a precaution. various flash prom vendors use slightly different interfaces to support both x8 and x16 modes. some vendors (intel, micron, some stmi- croelectronics devices) use a straightforward interface with pin naming that matches the fpga connections. however, the prom?s a0 pin is wasted in x16 applications and a sep- arate fpga user-i/o pin is required for the d15 data line. fortunately, the fpga a0 pin is still available as a user i/o after configuration, even though it connects to the flash prom. other vendors (amd, atmel, silicon storage technology, some stmicroelectronics devices) use a pin-efficient inter- face but change the function of one pin, called io15/a-1, depending if the prom is in x8 or x16 mode. in x8 mode, byte# = 0, this pin is the least-significant address line. the a0 address line selects the halfword location. the a-1 address line selects the byte location. when in x16 mode, byte# = 1, the io15/a-1 pin becomes the most-significant data bit, d15 because byte addressing is not required in this mode. check to see if the flash prom has a pin named ?io15/a-1" or "dq15/a-1". if so, be careful to connect x8/x16 flash proms correctly, as shown in ta b l e 5 4 . also, remember that the d[14:8] data connections require fpga user i/o pins but that the d15 data is already connected for the fpga?s a0 pin. table 53: maximum configrate settings for parallel flash proms flash read access time maximum configrate setting < 200 ns 3 < 90 ns 6 d functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 77 advance product specification r daisy-chaining if the application requires multiple fpgas with different con- figurations, then configure the fpgas using a daisy chain, as shown in figure 56 . use bpi mode (m[2:0] = <0:1:0> or <0:1:1>) for the fpga connected to the parallel nor flash prom and slave parallel mode (m[2:0] = <1:1:0>) for all other fpgas in the daisy-chain. after the master fpga?the fpga on the left in the diagram?finishes load- ing its configuration data from the parallel flash prom, the master device continues generating addresses to the flash prom and asserts its cso_b output low, enabling the next fpga in the daisy-chain. the next fpga then receives parallel configuration data from the flash prom. the mas- ter fpga?s cclk output synchronizes data capture. the downstream devices in slave parallel mode also actively drive their ldc[2:0] and hdc outputs during config- uration, although these signal are not used for configura- tion. these pins are in i/o bank 1, powered by vcco_1. because these pins do not connect elsewhere in the config- uration circuit, the voltage on vcco_1 can be whatever is required by the end application. table 54: fpga connections to flash prom with "io15/a-1" pin fpga pin connection to flash prom with io15/a-1 pin x8 flash prom interface after fpga configuration x16 flash prom interface after fpga configuration ldc2 byte# drive ldc2 low or leave unconnected and tie prom byte# input to gnd drive lcd2 high ldc1 oe# active-low flash prom output-enable control active-low flash prom output-enable control ldc0 cs# active-low flash prom chip-select control active-low flash prom chip-select control hdc we# flash prom write-enable control flash prom write-enable control a[23:1] a[n:0] a[n:0] a[n:0] a0 io15/a-1 io15/a-1 is least-significant address input io15/a-1 is most-significant data line, io15 d[7:0] io[7:0] io[7:0] io[7:0] user i/o upper data lines io[14:8] not required unless used as x16 flash interface after configuration upper data lines io[14:8] not required io[14:8] functional description 78 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r in-system programming support in a production application, the parallel flash prom is usually preprogrammed before it is mounted on the printed circuit board. in-system programming support is available from third-party boundary-scan tool vendors and from some third-party prom programmers using a socket adapter with attached wires. to gain access to the parallel flash signals, drive the fpga?s prog_b input low with an open-drain driver. this action places all fpga i/o pins, including those attached to the parallel flash, in high-impedance (hi-z). if the hswap input is high, the i/os have pull-up resistors to the v cco input on their respective i/o bank. the external programming hardware then has direct access to the paral- lel flash pins. the programming access points are high- lighted in the gray boxes in figure 55 and figure 56 . the fpga itself can also be used as a parallel flash prom programmer during development and test phases. initially, an fpga-based programmer is downloaded into the fpga via jtag. then the fpga performs the flash prom pro- gramming algorithms and receives programming data from the host via the fpga?s jtag interface. see chapter 11 in " embedded system tools reference manual ". dynamically loading multiple configuration images using multiboot option after the fpga configures itself using bpi mode from one end of the parallel flash prom, then the fpga can trigger a multiboot event and reconfigure itself from the opposite end of the parallel flash prom. multiboot is only available when using bpi mode and only for applications with a single spartan-3e fpga. by default, multiboot mode is disabled. to trigger a multi- boot event, assert a low pulse lasting at least 300 ns on the multiboot trigger (mbt) input to the startup_spartan3e library primitive . figure 57 shows an example usage. at power up, the fpga loads itself from the attached parallel flash prom. in this example, the m0 mode pin is low so the fpga starts at address 0 and increments through the flash prom memory locations. after the fpga completes configuration, the application loaded into the fpga per- forms a board-level or system test using fpga logic. if the test is successful, the fpga triggers a multiboot event, causing the fpga to reconfigure from the opposite end of the flash prom memory. this second configuration con- tains the fpga application for normal operation. figure 56: daisy-chaining from bpi flash mode +2.5v tdi tdo tms tck vccint vccaux +2.5v hdc cclk cso_b vcco_1 init_b csi_b d[7:0] ldc1 ldc0 ? a[16:0] prog_b done gnd vcco_2 +1.2v dq[7:0] a[n:0] ce# we# vcc oe# byte# dq[15:7] gnd m2 m1 ? ? m0 hswap vcco_0 a a[23:17] p ldc2 tdi tdo tms tck vccint vccaux hdc cclk cso_b vcco_1 init_b csi_b d[7:0] ldc1 ldc0 prog_b done gnd vcco_2 +1.2v m2 m1 ? ? m0 hswap vcco_0 p ldc2 vcco_1 +2.5v ? vcco_0 v v v v d v bpi mode slave parallel mode 2.5v jtag cclk d[7:0] init_b done prog_b tck tms x8 or x8/x16 flash prom prog_b recommend open-drain driver vcco_0 tdi tms tck tdo rdwr_b ? cso_b rdwr_b ? busy spartan-3e fpga spartan-3e fpga busy i 330 4.7k 4.7k not available in vq100 package ds312-2_50_021405 i functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 79 advance product specification r similarly, the general fpga application could trigger a multiboot event at any time to reload the diagnostics design. in another potential application, the initial design loaded into the fpga image contains a ?golden? or ?fail-safe? configura- tion image, which then communicates with the outside world and checks for a newer image. if there is a new configura- tion revision and the new image verifies as good, the ?golden? configuration triggers a multiboot event to load the new image. when a multiboot event is triggered, the fpga then again drives its configuration pins as described in ta bl e 5 1 . how- ever, the fpga does not assert the prog_b pin. the sys- tem design must ensure that no other device drives on these same pins during the reconfiguration process. the fpga?s done, ldc[2:0], or hdc pins can temporarily dis- able any conflicting drivers during reconfiguration. slave parallel mode in slave parallel mode (m[2:0] = <1:1:0>), an external host such as a microprocessor or microcontroller writes byte-wide configuration data into the fpga, using a typical peripheral interface as shown in figure 58 . figure 57: use multiboot to load alternate configuration images gsr gts mbt clk startup_spartan3e 0 ffffff general fpga application diagnostics fpga application parallel flash prom > 300 ns user area 0 ffffff general fpga application diagnostics fpga application parallel flash prom user area first configuration second configuration reconfigure ds312-2_51_021405 functional description 80 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the external download host starts the configuration process by pulsing prog_b and monitoring that the init_b pin goes high, indicating that the fpga is ready to receive its first data. the host asserts the active-low chip-select signal (csi_b) and the active-low write signal (rdwr_b). the host then continues supplying data and clock signals until either the fpga?s done pin goes high, indicating a suc- cessful configuration, or until the fpga?s init_b pin goes low, indicating a configuration error. the fpga captures data on the rising cclk edge. if the cclk frequency exceeds 50 mhz, then the host must also monitor the fpga?s busy output. if the fpga asserts busy high, the host must hold the data for an additional clock cycle, until busy returns low. if the cclk frequency is 50 mhz or below, the busy pin may be ignored but actively drives during configuration. the configuration process requires more clock cycles than indicated from the configuration file size. additional clocks are required during the fpga?s start-up sequence, espe- cially if the fpga is programmed to wait for selected digital clock managers (dcms) to lock to their respective clock inputs (see start-up , page 91 ). if the slave parallel interface is only used to configure the fpga, never to read data back, then the rdwr_b signal can also be eliminated from the interface. however, rdwr_b must remain low during configuration. figure 58: slave parallel configuration mode +2.5v prog_b recommend open-drain driver +2.5v jtag tdi tms tck tdo d[7:0] busy select read/write clock prog_b init_b done tdi tdo tms tck vccint vccaux hdc cso_b vcco_1 init_b csi_b ldc1 ldc0 prog_b done gnd vcco_2 +1.2v m2 m1 ? ? m0 hswap vcco_0 p ldc2 cclk d[7:0] ? vcco_0 v rdwr_b spartan-3e fpga busy slave parallel mode vcco_1 v v 4.7k +2.5v 330 ? 4.7k ? vcc gnd configuration memory source ? internal memory ? disk drive ? over network ? over rf link intelligent download host ? microcontroller ? processor ? tester ? computer ds312-2_52_022205 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 81 advance product specification r after configuration, all of the interface pins except done and prog_b are available as user i/os. alternatively, the bidirectional selectmap configuration interface is available after configuration. to continue using selectmap mode, set the persist bitstream generator option to yes . the external host can then read and verify configuration data. the slave parallel mode is also used with bpi mode to cre- ate multi-fpga daisy-chains. the lead fpga is set for bpi mode configuration; all the downstream daisy-chain fpgas are set for slave parallel configuration, as highlighted in figure 56 . table 55: slave parallel mode connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-ups during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. m2=1, m1=1, m0=0 sampled when init_b goes high. user i/o d[7:0] input data input . byte-wide data provided by host. fpga captures data on rising cclk edge. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. busy output busy indicator . if cclk frequency is < 50 mhz, this pin may be ignored. when high, indicates that the fpga is not ready to receive additional configuration data. host must hold data an additional clock cycle. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. csi_b input chip select input . active low. must be low throughout configuration. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. rdwr_b input read/write control . active low write enable. must be low throughout configuration. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. cclk input configuration clock . if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. external clock. user i/o if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. ldc[2:0] output low during configuration . these pins are not used during configuration. low throughout configuration. user i/o hdc output high during configuration . this pin is not used during configuration. high throughout configuration. user i/o functional description 82 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r voltage compatibility most slave parallel interface signals are within the fpga?s i/o bank 2, supplied by the vcco_2 supply input. the vcco_2 voltage can be 1.8v, 2.5v, or 3.3v to match the requirements of the external host, ideally 2.5v. using 1.8v or 3.3v requires additional design considerations as the done and prog_b pins are powered by the fpga?s 2.5v vccaux supply. see application note xapp453 : "the 3.3v configuration of spartan-3 fpgas" for additional infor- mation. the ldc[2:0] and hdc signal are active in i/o bank 1 but are not used in the interface. consequently, vcco_1 can be set the appropriate voltage for the application. daisy-chaining if the application requires multiple fpgas with different con- figurations, then configure the fpgas using a daisy chain. use slave parallel mode (m[2:0] = <1:1:0>) for all fpgas in the daisy-chain. the schematic in figure 59 is optimized for fpga downloading and does not support the selectmap read interface. the fpga?s rdwr_b pin must be low dur- ing configuration. after the lead fpga is filled with its configuration data, the lead fpga enables the next fpga in the daisy-chain by asserting is chip-select output, cso_b. cso_b output chip select output . active low. not used in single fpga applications. in a daisy-chain configuration, this pin connects to the csi_b pin of the next fpga in the chain. actively drives. user i/o init_b open-drain bidirectional i/o initialization indicator . active low. goes low at start of configuration during initialization memory clearing process. released at end of memory clearing, when mode select pins are sampled. in daisy-chain applications, this signal requires an external 4.7 k ? pull-up resistor to vcco_2. active during configuration. if crc error detected during configuration, fpga drives init_b low. user i/o done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully completes configuration. requires external 330 ? pull-up resistor to 2.5v. low indicates that the fpga is not yet configured. pulled high via external pull-up. when high, indicates that the fpga successfully configured. prog_b input program fpga . active low. when asserted low for 300 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. requires external 4.7 k ? pull-up resistor to 2.5v. if driving externally, use an open-drain or open-collector driver. must be high to allow configuration to start. drive prog_b low and release to reprogram fpga. table 55: slave parallel mode connections (continued) pin name fpga direction description during configuration after configuration v functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 83 advance product specification r slave serial mode in slave serial mode (m[2:0] = <1:1:1>), an external host such as a microprocessor or microcontroller writes serial configuration data into the fpga, using the synchronous serial interface shown in figure 60 . the serial configuration data is presented on the fpga?s din input pin with suffi- cient setup time before each rising edge of the externally generated cclk clock input. the intelligent host starts the configuration process by puls- ing prog_b and monitoring that the init_b pin goes high, indicating that the fpga is ready to receive its first data. the host then continues supplying data and clock signals until either the done pin goes high, indicating a successful configuration, or until the init_b pin goes low, indicating a configuration error. the configuration process requires more clock cycles than indicated from the configuration file size. additional clocks are required during the fpga?s start-up sequence, especially if the fpga is programmed to wait for selected digital clock managers (dcms) to lock to their respective clock inputs (see start-up , page 91 ). figure 59: daisy-chaining using slave parallel mode +2.5v prog_b recommend open-drain driver 2.5v jtag tdi tms tck tdo data[7:0] busy select read/write clock prog_b init_b done init_b done prog_b tck tms cso_b tdi tdo tms tck vccint vccaux hdc cso_b vcco_1 init_b csi_b ldc1 ldc0 prog_b done gnd vcco_2 +1.2v m2 m1 ? ? m0 hswap vcco_0 p ldc2 cclk d[7:0] ? vcco_0 v rdwr_b busy slave parallel mode vcco_1 tdi tdo tms tck vccint vccaux hdc cso_b vcco_1 init_b csi_b ldc1 ldc0 prog_b done gnd vcco_2 +1.2v m2 m1 ? ? m0 hswap vcco_0 p ldc2 cclk d[7:0] ? vcco_0 v rdwr_b spartan-3e fpga spartan-3e fpga busy slave parallel mode vcco_1 +2.5v v d[7:0] cclk +2.5v 330 ? 4.7k ? vcc gnd configuration memory source ? internal memory ? disk drive ? over network ? over rf link intelligent download host ? microcontroller ? processor ? tester ? ? v 4.7k ? ds312-2_53_022305 functional description 84 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the mode select pins, m[2:0], are sampled when the fpga?s init_b output goes high and must be at defined logic levels during this time. after configuration, when the fpga?s done output goes high, the mode pins are avail- able as full-featured user-i/o pins. similarly, the fpga?s hswap pin must be low to enable pull-up resistors on all user-i/o pins or high to dis- able the pull-up resistors. the hswap control must remain at a constant logic level throughout fpga configuration. after configuration, when the fpga?s done output goes high, the hswap pin is available as full-featured user-i/o pin and is powered by the vcco_0 supply. figure 60: slave serial configuration +2.5v tdi tdo tms tck vccint vccaux +2.5v vcco_2 init_b prog_b done gnd +1.2v hswap vcco_0 p vcco_0 4.7k ? spartan-3e fpga +2.5v jtag prog_b recommend open-drain driver tdi tms tck tdo m2 m1 ? ? m0 ? dout 330 ? din cclk v slave serial mode 4.7k ? v clock serial_out prog_b init_b done v vcc gnd configuration memory source ? internal memory ? disk drive ? over network ? over rf link intelligent download host ? microcontroller ? processor ? tester ? computer ds312-2_54_022305 p functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 85 advance product specification r voltage compatibility most slave serial interface signals are within the fpga?s i/o bank 2, supplied by the vcco_2 supply input. the vcco_2 voltage can be 3.3v, 2.5v, or 1.8v to match the requirements of the external host, ideally 2.5v. using 3.3v or 1.8v requires additional design considerations as the done and prog_b pins are powered by the fpga?s 2.5v vccaux supply. see application note xapp453 : "the 3.3v configuration of spartan-3 fpgas" for additional infor- mation. daisy-chaining if the application requires multiple fpgas with different con- figurations, then configure the fpgas using a daisy chain, as shown in figure 61 . use slave serial mode (m[2:0] = <1:1:1>) for all fpgas in the daisy-chain. after the lead fpga is filled with its configuration data, the lead fpga passes configuration data via its dout output pin to the next fpga on the falling cclk edge. table 56: slave serial mode connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-up during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. m2 = 1, m1 = 1, m0 = 1 sampled when init_b goes high. user i/o din input data input . serial data provided by host. fpga captures data on rising cclk edge. user i/o cclk input configuration clock . if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. external clock. user i/o init_b open-drain bidirectional i/o initialization indicator . active low. goes low at start of configuration during initialization memory clearing process. released at end of memory clearing, when mode select pins are sampled. in daisy-chain applications, this signal requires an external 4.7 k ? pull-up resistor to vcco_2. active during configuration. if crc error detected during configuration, fpga drives init_b low. user i/o done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully completes configuration. requires external 330 ? pull-up resistor to 2.5v. low indicates that the fpga is not yet configured. pulled high via external pull-up. when high, indicates that the fpga successfully configured. prog_b input program fpga . active low. when asserted low for 300 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. requires external 4.7 k ? pull-up resistor to 2.5v. if driving externally, use an open-drain or open-collector driver. must be high to allow configuration to start. drive prog_b low and release to reprogram fpga. v functional description 86 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r jtag mode the spartan-3e fpga has a dedicated four-wire ieee 1149.1/1532 jtag port that is always available any time the fpga is powered and regardless of the mode pin settings. however, when the fpga mode pins are set for jtag mode (m[2:0] = <1:0:1>), the fpga waits to be configured via the jtag port after a power-on event or when prog_b is asserted. selecting the jtag mode simply disables the other configuration modes. no other pins are required as part of the configuration interface. figure 62 illustrates a jtag-only configuration interface. the jtag interface is easily cascaded to any number of fpgas by connecting the tdo output of one device to the tdi input of the next device in the chain. the tdo output of the last device in the chain loops back to the port connector. figure 61: daisy-chaining using slave serial mode +2.5v tdi tdo tms tck vccint vccaux +2.5v vcco_2 init_b prog_b done gnd +1.2v hswap vcco_0 p tdi tdo tms tck vccint vccaux din dout vcco_2 init_b prog_b done gnd +1.2v m2 m1 ? ? m0 hswap vcco_0 p vcco_2 +2.5v ? vcco_0 4.7k +2.5v jtag cclk init_b done prog_b tck tms prog_b recommend open-drain driver vcco_0 tdi tms tck tdo m2 m1 ? ? m0 ? dout spartan-3e fpga spartan-3e fpga dout cclk 330 din cclk v slave serial mode slave serial mode 4.7k v clock serial_out prog_b init_b done v vcc gnd configuration memory source ? internal memory ? disk drive ? over network ? over rf link intelligent download host ? microcontroller ? processor ? tester ? computer ds312-2_55_022305 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 87 advance product specification r voltage compatibility the 2.5v vccaux supply powers the jtag interface. all of the user i/os are separately powered by their respective vcco_# supplies. when connecting the spartan-3e jtag port to a 3.3v inter- face, the jtag input pins must be current-limited to 10 ma or less using series resistors. similarly, the tdo pin is a cmos output powered from +2.5v. the tdo output can directly drive a 3.3v input but with reduced noise immunity. see application note xapp453 : "the 3.3v configuration of spartan-3 fpgas" for additional information. maximum bitstream size for daisy-chains the maximum bitstream length supported by spartan-3e fpgas in serial daisy-chains is 4,294,967,264 bits (4 gbits), roughly equivalent to a daisy-chain with 720 xc3s1600e fpgas. this is a limit only for serial daisy-chains where configuration data is passed via the fpga?s dout pin. there is no such limit for jtag chains. configuration sequence the spartan-3e configuration process is three-stage pro- cess that begins after the fpga powers on (a por event) or after the prog_b input is asserted. power-on reset (por) occurs after the v ccint , v ccaux , and the v cco bank 2 supplies reach their respective input threshold levels. after either a por or prog_b event, the three-stage con- figuration process begins. 1. the fpga clears (initializes) the internal configuration memory. 2. configuration data is loaded into the internal memory. 3. the user-application is activated by a start-up process. figure 63 is a generalized block diagram of the spartan-3e configuration logic, showing the interaction of different device inputs and bitstream generator (bitgen) options. a flow diagram for the configuration sequence of the serial and parallel modes appears in figure 64 . figure 65 shows the boundary-scan or jtag configuration sequence. initialization configuration automatically begins after power-on or after asserting the fpga prog_b pin, unless delayed using the fpga?s init_b pin. the fpga holds the open-drain init_b signal low while it clears its internal configuration memory. externally holding the init_b pin low forces the configura- tion sequencer to wait until init_b again goes high. figure 62: jtag configuration mode tdi tdo tms tck vccint vccaux +2.5v vcco_2 prog_b done gnd +1.2v hswap vcco_0 p vcco_0 spartan-3e fpga +2.5v jtag tck tms spartan-3e fpga tdi tms tck tdo m2 m1 ? ? m0 ? jtag mode vcco_2 tdi tdo tms tck vccint vccaux +2.5v vcco_2 prog_b done gnd +1.2v hswap vcco_0 p vcco_0 m2 m1 ? ? m0 ? jtag mode vcco_2 ds312-2_56_021405 functional description 88 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r figure 63: generalized spartan-3e fpga configuration logic block diagram ds312-2_57_022405 vcco_2 v cco2t vccint v ccintt vccaux v ccauxt prog_b cclk tck internal oscillator m1 m2 configrate reset reset enable reset enable done gts gsr gwe done_cycle gwe_cycle gts_cycle dcms_locked startupclk 0 0 1 1 initialization configuration startup user_clock internal_configuration_clock jtag_clock clear internal cmos configuration latches load application data into cmos configuration latches enable application logic and i/o pins init_b enable configuration error detection (crc checker) enable crc error power_good option = bitstream generator (bitgen) option dcm in user application locked startup_wait=true lck_cycle drivedone donepipe option = design attribute all dcms wait done done clearing_memory glitch filter done wait force all i/os hi- z hold all storage elements reset disable write operations to storage elements gts_in gsr_in user user * * * * these connections are available via the startup_spartan3e library primitive. en en power on reset (por) functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 89 advance product specification r figure 64: general configuration process sample mode pins no no no yes yes yes clear configuration memory power-on set prog_b low after power-on yes no crc correct? yes no reconfigure? load configuration data frames init_b goes low. abort start-up start-up sequence user mode init_ b = high? prog_b = low ds312-2_58_021404 v ccint >1v and v ccaux > 2v and v cco bank 4 > 1v m[2:0] and vs[2:0] pins are sampled on init_b rising edge done pin goes high, signaling end of configuration functional description 90 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r figure 65: boundary-scan configuration flow diagram sample mode pins (jtag port becomes available) clear configuration memory no no no yes yes yes yes no no power-on crc correct? load cfg_in instruction reconfigure? load jstart instruction synchronous tap reset (clock five 1's on tms) start-up sequence user mode init_b = high? prog_b = low load jprog instruction yes load configuration data frames v ccint >1v and v ccaux > 2v and v cco bank 4 > 1v init_b goes low. abort start-up set prog_b low after power-on ds312-2_59_022505 functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 91 advance product specification r the fpga signals when the memory-clearing phase is complete by releasing the open-drain init_b pin, allowing the pin to go high via the external pull-up resistor to vcco_2. loading configuration data configuration data is then written to the fpga?s internal memory. the fpga holds the global set/reset (gsr) sig- nal active throughout configuration, holding all fpga flip-flops in a reset state. the fpga signals when the entire configuration process completes be releasing the done pin, allowing it to go high. the fpga configuration sequence can also be initiated by asserting the prog_b. once release, the fpga begins clearing its internal configuration memory, and progresses through the remainder of the configuration process. start-up at the end of configuration, the global set/reset (gsr) sig- nal is pulsed, placing all flip-flops in a known state. after configuration completes, the fpga switches over to the user application loaded into the fpga. the sequence and timing of how the fpga switches over is programmable as is the clock source controlling the sequence. the default start-up sequence appears in figure 66 , where the global three-state signal (gts) is released one clock cycle after done goes high. this sequence allows the done signal to enable or disable any external logic used during configuration before the user application in the fpga starts driving output signals. one clock cycle later, the glo- bal write enable (gwe) signal is released. this allows sig- nals to propagate within the fpga before any clocked storage elements such as flip-flops and block rom are enabled. figure 66: default start-up sequence start-up clock default cycles sync-to-done 01 23 45 67 01 done high 23 45 67 phase start-up clock phase done gts gwe done gts gwe ds312-2_60_022305 functional description 92 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r the relative timing of configuration events is programmed via the bitstream generator (bitgen) options in the xilinx development software. for example, the gts and gwe events can be programmed to wait for all the done pins to high on all the devices in a multiple-fpga daisy-chain, forc- ing the fpgas to start synchronously. similarly, the start-up sequence can be paused at any stage, waiting for selected dcms to lock to their respective input clock signals. see also stabilizing dcm clocks before user mode , page 48 . the start-up sequence can by synchronized to a clock within the fpga application using the startup_spartan3e library primitive and by setting the startupclk bitstream generator option. the fpga applica- tion can optionally assert the global set/reset (gsr) and global three-state signal (gts) signals via the startup_spartan3e primitive. readb ack using slave parallel mode, configuration data from the fpga can be read back. readback is supported only in the slave parallel and jtag modes. along with the configuration data, it is possible to read back the contents of all registers, distributed ram, and block ram resources. this capability is used for real-time debug- ging. to synchronously control when registers values are cap- tured for readback, using the capture_spartan3 library primitive, which applies for both spartan-3 and spartan-3e fpga families. bitstream generator (bitgen) options various spartan-3e fpga functions are controlled by spe- cific bits in the configuration bitstream image. these values are specified when creating the bitstream image with the bitstream generator (bitgen) software. ta b l e 5 7 provides a list of all bitgen options for spartan-3e fpgas. table 57: spartan-3e fpga bitstream generator (bitgen) options option name pins/function affected values ( default ) description configrate cclk, configuration 3, 6 , 12, 25 sets the approximate frequency, in mhz, of the internal oscillator using for master serial, spi, and bpi configuration modes. the internal oscillator powers up at its lowest frequency and the new setting is loaded as part of the configuration bitstream. the software default value is 6 (~6 mhz). startupclk configuration, startup cclk default. the cclk signal (internally or externally generated) controls the startup sequence when the fpga transitions from configuration mode to the user mode. see start-up , page 91 . userclk a clock signal from within the fpga application controls the startup sequence when the fpga transitions from configuration mode to the user mode. see start-up , page 91 . the fpga application supplies the user clock on the clk pin on the startup_spartan3e primitive. jtag the jtag tck input controls the startup sequence when the fpga transitions from configuration mode to the user mode. see start-up , page 91 . unusedpin unused i/o pins pulldown default. all unused i/o pins have a pull-down resistor to gnd. pullup all unused i/o pins have a pull-up resistor to the vcco_# supply for its associated i/o bank. pullnone all unused i/o pins are left floating (hi-z, high-impedance, three-state). use external pull-up or pull-down resistors or logic to apply a valid signal level. done_cycle done pin, configuration startup 1, 2, 3, 4 , 5, 6 selects the configuration startup phase that activates the fpga?s done pin. see start-up , page 91 . functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 93 advance product specification r gwe_cycle all flip-flops, lut rams, and srl16 shift registers, block ram, configuration startup 1, 2, 3, 4, 5, 6 selects the configuration startup phase that asserts the internal write-enable signal to all flip-flops, lut rams and shift registers (srl16). it also enables block ram read and write operations. see start-up , page 91 . done waits for the done pin input to go high before asserting the internal write-enable signal to all flip-flops, lut rams and shift registers (srl16). block ram read and write operations are enabled at this time. keep retains the current gwe_cycle setting for partial reconfiguration applications. gts_cycle all i/o pins, configuration 1, 2, 3, 4, 5 , 6 selects the configuration startup phase that releases the internal three-state control, holding all i/o buffers in high-impedance (hi-z). output buffers actively drive, if so configured, after this point. see start-up , page 91 . done waits for the done pin input to go high before releasing the internal three-state control, holding all i/o buffers in high-impedance (hi-z). output buffers actively drive, if so configured, after this point. keep retains the current gts_cycle setting for partial reconfiguration applications. lck_cycle dcms, configuration startup nowait the fpga does not wait for selected dcms to lock before completing configuration. 0, 1, 2, 3, 4, 5, 6 if one or more dcms in the design have the startup_wait attribute set to true, the fpga waits for such dcms to acquire their respective input clock and assert their locked output. this setting selects the configuration startup phase where the fpga waits for the dcms to lock. donepin done pin pullup internally connects a pull-up resistor between done pin and vccaux. an external 330 ? pull-up resistor to vccaux is still recommended. pullnone no internal pull-up resistor on done pin. an external 330 ? pull-up resistor to vccaux is required. drivedone done pin no when configuration completes, the done pin stops driving low and relies on an external 330 ? pull-up resistor to vccaux for a valid logic high. yes when configuration completes, the done pin actively drives high. when using this option, an external pull-up resistor is no l onger required. only one device in an fpga daisy-chain should use this setting. donepipe done pin no the input path from done pin input back to the startup sequencer is not pipelined. yes this option adds a pipeline register stage between the done pin input and the startup sequencer. used for high-speed daisy-chain configurations when done cannot rise in a single cclk cycle. releases gwe and gts signals on the first rising edge of startupclk after the done pin input goes high. progpin prog_b pin pullup internally connects a pull-up resistor or between prog_b pin and vccaux. an external 4.7 k ? pull-up resistor to vccaux is still recommended. pullnone no internal pull-up resistor on prog_b pin. an external 4.7 k ? pull-up resistor to vccaux is required. tckpin jtag tck pin pullup internally connects a pull-up resistor between jtag tck pin and vccaux. pulldown internally connects a pull-down resistor between jtag tck pin and gnd. pullnone no internal pull-up resistor on jtag tck pin. tdipin jtag tdi pin pullup internally connects a pull-up resistor between jtag tdi pin and vccaux. pulldown internally connects a pull-down resistor between jtag tdi pin and gnd. pullnone no internal pull-up resistor on jtag tdi pin. table 57: spartan-3e fpga bitstream generator (bitgen) options (continued) option name pins/function affected values ( default ) description functional description 94 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r tdopin jtag tdo pin pullup internally connects a pull-up resistor between jtag tdo pin and vccaux. pulldown internally connects a pull-down resistor between jtag tdo pin and gnd. pullnone no internal pull-up resistor on jtag tdo pin. tmspin jtag tms pin pullup internally connects a pull-up resistor between jtag tms pin and vccaux. pulldown internally connects a pull-down resistor between jtag tms pin and gnd. pullnone no internal pull-up resistor on jtag tms pin. userid jtag user id register user string the 32-bit jtag user id register value is loaded during configuration. the default value is all ones, 0xffff_ffff hexadecimal. to specify another value, enter an 8-character hexadecimal value. security jtag, selectmap, readback, partial reconfiguration none readback and partial reconfiguration are available via the jtag port or via the selectmap interface, if the persist option is set to yes. level1 readback function is disabled. partial reconfiguration is still available via the jtag port or via the selectmap interface, if the persist option is set to yes. level readback function is disabled. partial reconfiguration is disabled. crc configuration enable default. enable crc checking on the fpga bitstream. if error detected, fpga asserts init_b low and done pin stays low. disable turn off crc checking. persist selectmap interface pins, bpi mode, slave mode, configuration no all bpi and slave mode configuration pins are available as user-i/o after configuration. yes this option is required for readback and partial reconfiguration using the selectmap interface. the selectmap interface pins (see slave parallel mode , page 79 ) are reserved after configuration and are not available as user-i/o. table 57: spartan-3e fpga bitstream generator (bitgen) options (continued) option name pins/function affected values ( default ) description functional description ds312-2 (v1.1) march 21, 2005 www.xilinx.com 95 advance product specification r powering spartan-3e fpgas voltage supplies like spartan-3 fpgas, spartan-3e fpgas have multiple voltage supply inputs, as shown in ta b l e 5 8 . there are two supply inputs for internal logic functions, v ccint and v ccaux . each of the four i/o banks has a separate v cco supply input that powers the output buffers within the asso- ciated i/o bank. all of the v cco connections to a specific i/o bank must be connected and must connect to the same voltage. in a 3.3v-only application, all four v cco supplies connect to 3.3v. however, spartan-3e fpgas provide the ability to bridge between different i/o voltages and standards by applying different voltages to the v cco inputs of different banks. refer to i/o banking rules for which i/o standards can be intermixed within a single i/o bank. each i/o bank also has an separate, optional input voltage reference supply, called vref. if the i/o bank includes an i/o standard that requires a voltage reference such as hstl or sstl, then all vref pins within the i/o bank must be connected to the same voltage. voltage regulators various power supply manufacturers offer complete power solutions for xilinx fpgas including some with integrated three-rail regulators specifically designed for spartan-3 and spartan-3e fpgas. the xilinx power corner web site pro- vides links to vendor solution guides and xilinx power esti- mation and analysis tools. power distribution syst em (pds) design and decoupling/bypa ss capacitors good power distribution system (pds) design is important for all fpga designs, but especially so for high performance applications, greater than 100 mhz. proper design results in better overall performance, lower clock and dcm jitter, and a generally more robust system. before designing the printed circuit board (pcb) for the fpga design, please review xapp623 : "power distribution system (pds) design: using bypass/decoupling capacitors". table 58: spartan-3e voltage supplies supply input description nominal supply voltag e vccint internal core supply voltage. supplies all internal logic functions such as clbs, block ram, multipliers, etc. input to power-on reset (por) circuit. 1.2v vccaux auxiliary supply voltage. supplies digital clock managers (dcms), differential drivers, dedicated configuration pins, jtag interface. input to power-on reset (por) circuit. 2.5v vcco_0 supplies the output buffers in i/o bank 0, the bank along the top edge of the fpga. selectable, 3.3v, 3.0v, 2.5v, 1.8, 1.5v, or 1.2v. vcco_1 supplies the output buffers in i/o bank 1, the bank along the right edge of the fpga. in byte-wide peripheral interface (bpi) parallel flash mode , connects to the save voltage as the flash prom. selectable, 3.3v, 3.0v, 2.5v, 1.8, 1.5v, or 1.2v. vcco_2 supplies the output buffers in i/o bank 2 the bank along the bottom edge of the fpga. connects to the same voltage as the fpga configuration source. input to power-on reset (por) circuit. selectable, 3.3v, 3.0v, 2.5v, 1.8, 1.5v, or 1.2v. vcco_3 supplies the output buffers in i/o bank 0, the bank along the top edge of the fpga. selectable, 3.3v, 3.0v, 2.5v, 1.8, 1.5v, or 1.2v. functional description 96 www.xilinx.com ds312-2 (v1.1) march 21, 2005 advance product specification r revision history the following table shows the revision history for this document. the spartan-3e family data sheet ds312-1, spartan-3e fpga family: introduction and ordering information (module 1) ds312-2, spartan-3e fpga family: functional description (module 2) ds312-3, spartan-3e fpga family: dc and switching characteristics (module 3) ds312-4, spartan-3e fpga family: pinout descriptions (module 4) date version revision 03/01/05 1.0 initial xilinx release. 03/21/05 1.1 updated figure 42 . modified title on ta b l e 3 3 and ta b l e 3 9 . ds312-3 (v1.0) march 1, 2005 www.xilinx.com 1 advance product specification ? 2005 xilinx, inc. all rights reserved. xilinx, the xilinx logo, and other designated brands included herein are trademarks of xilinx, inc. all other trademarks are the property of their respective owners. dc electrical characteristics in this section, specifications may be designated as advance, preliminary, or production. these terms are defined as follows: advance: initial estimates are based on simulation, early characterization, and/or extrapolation from the characteris- tics of other families. values are subject to change. use as estimates, not for production. preliminary: based on characterization. further changes are not expected. production: these specifications are approved once the silicon has been characterized over numerous production lots. parameter values are considered stable with no future changes expected. all parameter limits are representative of worst-case supply voltage and junction temperature conditions. the following applies unless otherwise noted: the parameter values published in this module apply to all spartan?-3e devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. if a particular spartan-3e fpga differs in functional behavior or electrical characteristic from this data sheet, those differences are described in a separate errata document. the errata documents for spartan-3e fpgas are living documents and are available online . 018 spartan-3e fpga family: dc and switching characteristics ds312-3 (v1.0) march 1, 2005 00 advance product specification r table 1: absolute maximum ratings symbol description conditions min max units v ccint internal supply voltage ?0.5 1.32 v v ccaux auxiliary supply voltage ?0.5 3.00 v v cco output driver supply voltage ?0.5 3.75 v v ref input reference voltage ?0.5 v cco +0.5 (3) v v in (2) voltage applied to all user i/o pins and dual-purpose pins driver in a high-impedance state ?0.5 v cco +0.5 (3) v voltage applied to all dedicated pins ?0.5 v ccaux +0.5 (4) v v esd electrostatic discharge voltage human body model ?2000 +2000 v charged device model ?500 +500 v machine model ?200 +200 v t j junction temperature - 125 c t stg storage temperature ?65 150 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only; functional operation of the device at these or any other conditions beyond those listed under the recommended operating conditi ons is not implied. exposure to absolute maximum ratings conditions for extended periods of time adversely affects device reliability. 2. as a rule, the v in limits apply to both the dc and ac components of signals. simple application solutions are available that show how to handle overshoot/undershoot as well as achieve pci compliance. refer to the following application notes: "virtex?-ii pro and sp artan-3 3.3v pci reference design" ( xapp653 ) and "using 3.3v i/o guidelines in a virtex-ii pro design" ( xapp659 ). 3. each of the user i/o and dual-purpose pins is associated with one of the four banks? v cco rails. meeting the v in max limit ensures that the internal diode junctions that exist between these pins and their associated v cco rails do not turn on. ta b l e 4 specifies the v cco range used to determine the max limit. when v cco is at its maximum recommended operating level (3.45v), v in max is 3.95v. the maximum voltage that avoids oxide stress is v inx = 4.05v. as long as the v in max specification is met, oxide stress is not possible. 4. all dedicated pins (prog_b, done, tck, tdi, tdo, and tms) draw power from the v ccaux rail (2.5v). meeting the v in max limit ensures that the internal diode junctions that exist between each of these pins and the v ccaux rail do not turn on. ta bl e 4 specifies the v ccaux range used to determine the max limit. when v ccaux is at its maximum recommended operating level (2.625v), v in max < 3.125v. as long as the v in max specification is met, oxide stress is not possible. 5. for soldering guidelines, see "device packaging and thermal characteristics" at www.xilinx.com/bvdocs/userguides/ug112.pdf . also see "implementation and solder reflow guidelines for pb-free packages" at www.xilinx.com/bvdocs/appnotes/xapp427.pdf . dc and switching characteristics 2 www.xilinx.com ds312-3 (v1.0) march 1, 2005 advance product specification r table 2: supply voltage thresholds for power-on reset symbol description min max units v ccintt threshold for the v ccint supply 0.4 1.0 v v ccauxt threshold for the v ccaux supply 0.8 2.0 v v cco2t threshold for the v cco bank 2 supply 0.4 1.0 v notes: 1. v ccint , v ccaux , and v cco supplies may be applied in any order. 2. to ensure successful power-on, v ccint , v cco bank 2, and v ccaux supplies must rise through their respective threshold-voltage ranges with no dips at any point. table 3: power voltage levels necessary for preserving ram contents symbol description min units v drint v ccint level required to retain ram data 1.0 v v draux v ccaux level required to retain ram data 2.0 v v dro v cco level required to retain ram data 1.0 v notes: 1. ram contents include configuration data. table 4: general recommended operating conditions symbol description min nom max units t j junction temperature commercial 0 - 85 c industrial ?40 - 100 c v ccint internal supply voltage 1.140 1.200 1.260 v v cco (1) output driver supply voltage 1.140 - 3.450 v v ccaux (2) auxiliary supply voltage 2.375 2.500 2.625 v notes: 1. the v cco range given here spans the lowest and highest operating voltages of all supported i/o standards. the recommended v cco range specific to each of the single-ended i/o standards is given in ta bl e 7 , and that specific to the differential standards is given in ta bl e 9 . 2. only during dcm operation, it is recommended that the rate of change of v ccaux not exceed 10 mv/ms. dc and switching characteristics ds312-3 (v1.0) march 1, 2005 www.xilinx.com 3 advance product specification r table 5: general dc characteristics of user i/o, dual-purpose, and dedicated pins symbol description test conditions min typ max units i l (2) leakage current at user i/o, dual-purpose, and dedicated pins driver is in a high-impedance state, v in = 0v or v cco max, sample-tested ?10 - +10 a i rpu (3) current through pull-up resistor at user i/o, dual-purpose, and dedicated pins v in = 0v, v cco = 3.3v ma v in = 0v, v cco = 3.0v ma v in = 0v, v cco = 2.5v ma v in = 0v, v cco = 1.8v ma v in = 0v, v cco = 1.5v ma v in = 0v, v cco = 1.2v ma i rpd (3) current through pull-down resistor at user i/o, dual-purpose, and dedicated pins v in = v cco ma i ref v ref current per pin all v cco levels ?10 - +10 a c in input capacitance 3 - 10 pf notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 4 . 2. the i l specification applies to every i/o pin throughout power-on as long as the voltage on that pin stays between the absolute v in minimum and maximum values ( ta bl e 1 ). for hot-swap applications, at the time of card connection, be sure to keep all i/o voltages within this range before applying v cco power. also consider applying v cco power before the connection of data lines occurs. when the fpga is completely unpowered, the impedance at the i/o pins is high. 3. this parameter is based on characterization. the pull-up resistance r pu = v cco / i rpu . the pull-down resistance r pd =v in /i rpd . dc and switching characteristics 4 www.xilinx.com ds312-3 (v1.0) march 1, 2005 advance product specification r table 6: quiescent supply current characteristics symbol description device typ (4) max units i ccintq quiescent v ccint supply current XC3S100E 15 ma xc3s250e 38 ma xc3s500e 68 ma xc3s1200e 98 ma xc3s1600e 108 ma i ccoq quiescent v cco supply current XC3S100E 1.0 ma xc3s250e 1.5 ma xc3s500e 1.7 ma xc3s1200e 1.8 ma xc3s1600e 2.2 ma i ccauxq quiescent v ccaux supply current XC3S100E 10 ma xc3s250e 15 ma xc3s500e 25 ma xc3s1200e 35 ma xc3s1600e 45 ma notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 4 . quiescent supply current is measured with all i/o drivers in a high-impedance state and with all pull-up/pull-down resistors at the i/o pads disabled. for typical values, the ambient tempera ture (t a ) is 25c with v ccint = 1.2v, v cco = 2.5v, and v ccaux = 2.5v. the fpga is programmed with a "blank" configuration data file (i.e., a design with no functional elements instantiated). for conditions other than those described above, (e.g., a design including functiona l elements), measured quiescent current levels may be higher than the values in the table. 2. there are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) the spartan-3e web power tool, a future web-based application, provides quick, approximate, typical estimates, and does not require a netlist of the design. b) xpower, which will be included in a future release of the xilinx development software, takes a netlist as inp ut to provide more accurate maximum and typical estimates. 3. the maximum numbers in this table indicate the minimum current each power rail requires in order for the fpga to power-on suc cessfully. 4. all typical quiescent current values are early estimates. dc and switching characteristics ds312-3 (v1.0) march 1, 2005 www.xilinx.com 5 advance product specification r table 7: recommended operating conditions for us er i/os using single-ended standards iostandard attribute v cco for drivers (2) v ref v il v ih min (v) nom (v) max (v) min (v) nom (v) max (v) max (v) min (v) hstl_i_18 1.7 1.8 1.9 0.8 0.9 1.1 v ref - 0.1 v ref + 0.1 hstl_iii_18 1.7 1.8 1.9 - 1.1 - v ref - 0.1 v ref + 0.1 lvcm os 12 (4) 1.1 1.2 1.3 - - - 0.38 0.8 lvcm os 15 (4) 1.4 1.5 1.6 - - - 0.38 0.8 lvcm os 18 (4) 1.65 1.8 1.95 - - - 0.38 0.8 lvcm os 25 (4,5) 2.3 2.5 2.7 - - -0.7 1.7 lvcm os 33 (4) 3.0 3.3 3.45 - - -0.8 2.0 lvttl 3.0 3.3 3.45 - - -0.8 2.0 pci33_3 (7) -3.0 - - - -0.9 1.5 pci66_3 (7) -3.0 - - - -0.9 1.5 pcix (7) -tbd - - - -tbd tbd sstl18_i 1.70 1.80 1.90 0.833 0.900 0.969 v ref - 0.125 v ref + 0.125 sstl2_i 2.3 2.5 2.7 1.15 1.25 1.35 v ref - 0.15 v ref + 0.15 notes: 1. descriptions of the symbols used in this table are as follows: v cco -- the supply voltage for output drivers v ref -- the reference voltage for setting the input switching threshold v il -- the input voltage that indicates a low logic level v ih -- the input voltage that indicates a high logic level 2. the v cco rails supply only output drivers, not input circuits. 3. for device operation, the maximum signal voltage (v ih max) may be as high as v in max. see ta bl e 1 . 4. there is approximately 100 mv of hysteresis on inputs using any lvcmos standard. 5. all dedicated pins (prog_b, done, tck, tdi, tdo, and tms) use the lvcmos25 standard and draw power from the v ccaux rail (2.5v). the dual-purpose configuration pins use the lvcmos25 standard before the user mode. when using these pins as part of a standard 2.5v configuration interface, apply 2.5v to the v cco lines of banks 0, 1, and 2 at power-on as well as throughout configuration. 6. the global clock inputs (gclk0-gclk15, rhclk0-rhclk7, and lhclk0-lhclk7) are dual-purpose pins to which any signal standard may be assigned. 7. for more information, see "virtex-ii pro and spartan-3 3.3v pci reference design" ( xapp653 ). dc and switching characteristics 6 www.xilinx.com ds312-3 (v1.0) march 1, 2005 advance product specification r table 8: dc characteristics of user i/os using single-ended standards iostandard attribute test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v) hstl_i_18 8 ?8 0.4 v cco - 0.4 hstl_iii_18 24 ?8 0.4 v cco - 0.4 lvcm os 12 (3) 22 ?2 0.4v cco - 0.4 lvcm os 15 (3) 22 ?2 0.4v cco - 0.4 44 ?4 66 ?6 lvcm os 18 (3) 22 ?2 0.4v cco - 0.4 44 ?4 66 ?6 88 ?8 lvcm os 25 (3,4) 22 ?2 0.4v cco - 0.4 44 ?4 66 ?6 88 ?8 12 12 ?12 lvcm os 33 (3) 22 ?2 0.4v cco - 0.4 44 ?4 66 ?6 88 ?8 12 12 ?12 16 16 ?16 lvttl (3) 22 ?2 0.4 2.4 44 ?4 66 ?6 88 ?8 12 12 ?12 16 16 ?16 pci33_3 (5) 1.5 ?0.5 0.10v cco 0.90v cco pci66_3 (5) 1.5 ?0.5 0.10v cco 0.90v cco pcix tbd tbd tbd tbd sstl18_i 6.7 ?6.7 v tt - 0.475 v tt + 0.475 dc and switching characteristics ds312-3 (v1.0) march 1, 2005 www.xilinx.com 7 advance product specification r sstl2_i 8.1 ?8.1 v tt - 0.61 v tt + 0.61 notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 4 and ta bl e 7 . 2. descriptions of the symbols used in this table are as follows: i ol -- the output current condition under which v ol is tested i oh -- the output current condition under which v oh is tested v ol -- the output voltage that indicates a low logic level v oh -- the output voltage that indicates a high logic level v il -- the input voltage that indicates a low logic level v ih -- the input voltage that indicates a high logic level v cco -- the supply voltage for output drivers v ref -- the reference voltage for setting the input switching threshold v tt -- the voltage applied to a resistor termination 3. for the lvcmos and lvttl standards: the same v ol and v oh limits apply for both the fast and slow slew attributes. 4. all dedicated output pins (done and tdo) as well as dual-purpose totem-pole output pins (cclk, d0-d7, busy/dout, cso_b, mosi, hdc, ldc0-ldc2, and a0-a23) exhibit the characteristics of lvcmos25 with slow slew rate; all have 8 ma drive except cclk, which has 12 ma drive. 5. tested according to the relevant pci specifications. for more information, see "virtex-ii pro and spartan-3 3.3v pci referenc e design" ( xapp653 ). table 8: dc characteristics of user i/os using single-ended standards (continued) iostandard attribute test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v) dc and switching characteristics 8 www.xilinx.com ds312-3 (v1.0) march 1, 2005 advance product specification r figure 1: differential input voltages ds099-3_01_012304 v inn v inp gnd level 50% v icm v icm = input common mode voltage = v id v inp internal logic differential i/o pair pins v inn n p 2 v inp + v inn v id = differential input voltage = v inp - v inn table 9: recommended operating conditions for user i/os using differential signal standards iostandard attribute v cco for drivers (1) v id v icm v ih v il min (v) nom (v) max (v) min (mv) nom (mv) max (mv) min (v) nom (v) max (v) min (v) max (v) min (v) max (v) lvds_25 2.3752.502.6251003506000.301.252.20---- blvds_25 2.3752.502.6251003506000.301.252.20---- mini_lvds_25 2.375 2.50 2.625 200 - 600 0.30 - 2.2 lvpecl_25 (2) inputs only 100 800 1000 0.3 1.2 2.2 0.8 2.0 0.5 1.7 rsds_25 2.3752.502.625100200-0.31.201.4---- notes: 1. the v cco rails supply only differential output drivers, not input circuits. 2. spartan-3e devices support this standard for inputs only, not for outputs. 3. v ref inputs are not used for any of the differential i/o standards. dc and switching characteristics ds312-3 (v1.0) march 1, 2005 www.xilinx.com 9 advance product specification r figure 2: differential output voltages ds312-3_03_021505 v outn v outp gnd level 50% v ocm v ocm v od v ol v oh v outp internal logic v outn n p = output common mode voltage = 2 v outp + v outn v od = output differential voltage = v oh = output voltage indicating a high logic level v ol = output voltage indicating a low logic level v outp - v outn differential i/o pair pins table 10: dc characteristics of user i/os using differential signal standards iostandard attribute v od ? v od v ocm ? v ocm v oh v ol min (mv) typ (mv) max (mv) min (mv) max (mv) min (v) typ (v) max (v) min (mv) max (mv) min (v) max (v) lvds_25 250 350 450 - - 1.125 - 1.375 - - 1.25 1.25 blvds_25 250 350 450 - - - 1.20 - - - - - mini_lvds_25 300 - 600 - 50 1.0 - 1.4 - 50 1.15 1.25 rsds_25 100 - 400 - - 1.1 - 1.4 - - 1.15 1.35 notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 4 and ta b l e 9 . 2. output voltage measurements for all differential standards are made with a termination resistor (r t ) of 100 ? across the n and p pins of the differential signal pair. 3. at any given time, no more than two differential standards may be assigned to each bank. dc and switching characteristics 10 www.xilinx.com ds312-3 (v1.0) march 1, 2005 advance product specification r switching characteristics all spartan-3e fpgas ship in two speed grades: ?4 and the higher performance ?5. switching characteristics in this document may be designated as advance, preliminary, or production, as shown in ta b l e 1 1 . each category is defined as follows: advance : these specifications are based on simulations only and are typically available soon after establishing fpga specifications. although speed grades with this des- ignation are considered relatively stable and conservative, some under-reporting might still occur. preliminary : these specifications are based on complete early silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under-reporting preliminary delays is greatly reduced compared to advance data. production : these specifications are approved once enough production silicon of a particular device family mem- ber has been characterized to provide full correlation between speed files and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typ- ically, the slowest speed grades transition to production before faster speed grades. production-quality systems must use fpga designs com- piled using a speed file designated as production status. fpgas designs using a less mature speed file designation should only be used during system prototyping or pre-pro- duction qualification. fpga designs with speed files desig- nated as preview, advance, or preliminary should not be used in a production-quality system. whenever a speed file designation changes, as a device matures toward production status, xilinx recommends rerunning the xilinx ise software on the fpga design. this ensures that the fpga design incorporates the latest timing information and software updates. all specified limits are representative of worst-case supply voltage and junction temperature conditions. unless other- wise noted, the following applies: parameter values apply to all spartan-3e devices. all parameters representing volt- ages are measured with respect to gnd. timing parameters and their representative values are selected for inclusion below either because they are impor- tant as general design requirements or they indicate funda- mental device performance characteristics. the spartan-3e speed files (v1.10), part of the xilinx development software, are the original source for many but not all of the values. the speed grade designations for these files are shown in ta b l e 1 1 . for more complete, more precise, and worst-case data, use the values reported by the xilinx static timing ana- lyzer (trace in the xilinx development software) and back-annotated to the simulation netlist. digital clock mana ger (dcm) timing for specification purposes, the dcm consists of three key components: the delay-locked loop (dll), the digital fre- quency synthesizer (dfs), and the phase shifter (ps). aspects of dll operation play a role in all dcm applica- tions. all such applications inevitably use the clkin and the clkfb inputs connected to either the clk0 or the clk2x feedback, respectively. thus, specifications in the dll tables ( ta b l e 1 2 and ta b l e 1 3 ) apply to any application that only employs the dll component. when the dfs and/or the ps components are used together with the dll, then the specifications listed in the dfs and ps tables super- sede any corresponding ones in the dll tables. (see ta b l e 1 4 and ta b l e 1 5 for the dfs; tables for the ps are not yet available.) dll specifications that do not change with the addition of dfs or ps functions are presented in ta b l e 1 2 and ta b l e 1 3 . all dcm clock output signals exhibit an approximate duty cycle of 50%. period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. both specifications describe statistical variation from a mean value. period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock peri- ods sampled (usually from 100,000 to more than a million samples for specification purposes). in a histogram of period jitter, the mean value is the clock period. cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock peri- ods sampled. in a histogram of cycle-cycle jitter, the mean value is zero. table 11: spartan-3e v1.10 speed grade designations device preview advance preliminary production XC3S100E ?4 xc3s250e ?4 xc3s500e ?4 xc3s1200e ?4 xc3s1600e ?4 system usage prototyping only production dc and switching characteristics ds312-3 (v1.0) march 1, 2005 www.xilinx.com 11 advance product specification r table 12: recommended operating conditions for the dll symbol description speed grade units -5 -4 min max min max input frequency ranges f clkin clkin_freq_dll frequency for the clkin input 5 326 5 (2) 280 mhz notes: 1. dll specifications apply when any of the dll outputs (clk0, clk90, clk180, clk270, clk2x, clk2x180, or clkdv) are in use. 2. use of the dfs permits lower f clkin frequencies. see ta bl e 1 4 . table 13: switching characteristics for the dll symbol description speed grade units -5 -4 min max min max output frequency ranges clkout_freq_1x frequency for the clk0 and clk180 outputs 5 326 5 280 mhz frequency for the clk90 and clk270 outputs 5 165 5 165 mhz clkout_freq_2x frequency for the clk2x and clk2x180 outputs 10 400 10 330 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 4 and ta bl e 1 2 . 2. dll specifications apply when any of the dll outputs (clk0, clk90, clk180, clk270, clk2x, clk2x180, or clkdv) are in use. dc and switching characteristics 12 www.xilinx.com ds312-3 (v1.0) march 1, 2005 advance product specification r table 14: recommended operating conditions for the dfs symbol description speed grade units -5 -4 min max min max input frequency ranges (2) f clkin clkin_freq_fx frequency for the clkin input 0.2 326 0.2 326 mhz notes: 1. dfs specifications apply when either of the dfs outputs (clkfx or clkfx180) are in use. 2. if both dfs and dll outputs are used on the same dcm, follow the more restrictive clkin_freq_dll specifications in ta bl e 1 2 . table 15: switching characteristics for the dfs symbol description speed grade units -5 -4 min max min max output frequency ranges clkout_freq_fx frequency for the clkfx and clkfx180 outputs 5 326 5 280 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 4 and ta b l e 1 4 . 2. dfs specifications apply when either of the dfs outputs (clkfx or clkfx180) is in use. dc and switching characteristics ds312-3 (v1.0) march 1, 2005 www.xilinx.com 13 advance product specification r configuration and jtag timing figure 3: waveforms for power-on and the beginning of configuration table 16: power-on timing and the beginning of configuration symbol description device all speed grades units min max t por (2) the time from the application of v ccint , v ccaux , and v cco bank 2 supply voltage ramps (whichever occurs last) to the rising transition of the init_b pin XC3S100E - 5 ms xc3s250e - 5 ms xc3s500e - 5 ms xc3s1200e - 5 ms xc3s1600e - 7 ms t prog the width of the low-going pulse on the prog_b pin all 0.3 - s t pl (2) the time from the rising edge of the prog_b pin to the rising transition on the init_b pin XC3S100E - 2 ms xc3s250e - 2 ms xc3s500e - 2 ms xc3s1200e - 2 ms xc3s1600e - 3 ms t icck (3) the time from the rising edge of the init_b pin to the generation of the configuration clock signal at the cclk output pin all 0.5 4.0 s notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 4 . this means power must be applied to all v ccint , v cco , and v ccaux lines. 2. power-on reset and the clearing of configuration memory occurs during this period. 3. this specification applies only to the master serial, spi, bpi-up, and bpi-down modes. v ccint (supply) (supply) (supply) v ccaux v cco bank 2 prog_b (output) (open-drain) (input) init_b cclk ds312-3_01_020505 1.2v 2.5v t icck t prog t pl t por 1.0v 1.0v 2.0v notes: 1. the v ccint , v ccaux , and v cco supplies may be applied in any order. 2. the low-going pulse on prog_b is optional after power-on but necessary for reconfiguration without a power cycle. 3. the rising edge of init_b samples the voltage levels applied to the mode pins (m0 - m2). dc and switching characteristics 14 www.xilinx.com ds312-3 (v1.0) march 1, 2005 advance product specification r figure 4: waveforms for master and slave serial configuration table 17: timing for the master and slav e serial configuration modes symbol description slave/ master all speed grades units min max clock-to-output times t cco the time from the falling transition on the cclk pin to data appearing at the dout pin both 1.5 12.0 ns setup times t dcc the time from the setup of data at the din pin to the rising transition at the cclk pin both 10.0 - ns hold times t ccd the time from the rising transition at the cclk pin to the point when data is last held at the din pin both 0 - ns clock timing t cch the high pulse width at the cclk input pin slave 5.0 - ns t ccl the low pulse width at the cclk input pin 5.0 - ns f ccser frequency of the clock signal at the cclk input pin no bitstream compression - 66 (2) mhz with bitstream compression - 20 mhz ? f ccser variation from the cclk output frequency set using the configrate bitgen option master ?50% +50% - notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 4 . 2. for serial configuration with a daisy-chain of multiple fpgas, the maximum limit is 25 mhz. ds099-3_04_071604 bit 0 bit 1 bit n bit n+1 bit n-64 bit n-63 1/f ccser t ccl t dcc t ccd t cch t cco prog_b (input) din (input) dout (output) (open-drain) init_b (input/output) cclk dc and switching characteristics ds312-3 (v1.0) march 1, 2005 www.xilinx.com 15 advance product specification r figure 5: waveforms for slave parallel configuration ds312-3_02_020805 byte 0 byte 1 byte n busy high-z high-z byte n+1 t smwcc 1/f ccpar t smcccs t ccl t smckby t smckby t cch t smccw t smccd t smcscc t smdcc prog_b (input) (open-drain) init_b (input) cs_b (output) busy rdwr_b (input) (input) cclk (inputs) d0 - d7 notes: 1. it is possible to abort configuration by pulling cs_b low in a given cclk cycle, then switching rdwr_b low or high in any sub sequent cycle for which cs_b remains low. the rdwr_b pin asynchronously controls the driver impedance of the d0 - d7 bus. when rdwr_b switches high, be careful to avoid contention on the d0 - d7 bus. table 18: timing for the slave parallel configuration mode symbol description all speed grades units min max clock-to-output times t smckby the time from the rising transition on the cclk pin to a signal transition at the busy pin -12.0ns setup times t smdcc the time from the setup of data at the d0-d7 pins to the rising transition at the cclk pin 10.0 - ns t smcscc the time from the setup of a logic level at the cs_b pin to the rising transition at the cclk pin 10.0 - ns t smccw (2) the time from the setup of a logic level at the rdwr_b pin to the rising transition at the cclk pin 10.0 - ns dc and switching characteristics 16 www.xilinx.com ds312-3 (v1.0) march 1, 2005 advance product specification r hold times t smccd the time from the rising transition at the cclk pin to the point when data is last held at the d0-d7 pins 0-ns t smcccs the time from the rising transition at the cclk pin to the point when a logic level is last held at the cs_b pin 0-ns t smwcc the time from the rising transition at the cclk pin to the point when a logic level is last held at the rdwr_b pin 0-ns clock timing t cch the high pulse width at the cclk input pin 5 - ns t ccl the low pulse width at the cclk input pin 5 - ns f ccpar frequency of the clock signal at the cclk input pin no bitstream compression not using the busy pin (2) -50mhz using the busy pin - 66 mhz with bitstream compression - 20 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 4 . 2. in the slave parallel mode, it is necessary to use the busy pin when the cclk frequency exceeds this maximum specification. 3. some xilinx documents may refer to parallel modes as "selectmap" modes. table 18: timing for the slave parallel configuration mode (continued) symbol description all speed grades units min max dc and switching characteristics ds312-3 (v1.0) march 1, 2005 www.xilinx.com 17 advance product specification r figure 6: jtag waveforms tck t tmstck tms tdi tdo (input) (input) (input) (output) t tcktms t tcktdi t tcktdo t tditck ds099_06_040703 t cch t ccl 1/f tck table 19: timing for the jtag test access port symbol description all speed grades units min max clock-to-output times t tcktdo the time from the falling transition on the tck pin to data appearing at the tdo pin 1.0 11.0 ns setup times t tditck the time from the setup of data at the tdi pin to the rising transition at the tck pin 7.0 - ns t tmstck the time from the setup of a logic level at the tms pin to the rising transition at the tck pin 7.0 - ns hold times t tcktdi the time from the rising transition at the tck pin to the point when data is last held at the tdi pin 0-ns t tcktms the time from the rising transition at the tck pin to the point when a logic level is last held at the tms pin 0-ns clock timing t cch the high pulse width at the tck pin 5 - ns t ccl the low pulse width at the tck pin 5 - ns f tck frequency of the tck signal - 33 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 4 . dc and switching characteristics 18 www.xilinx.com ds312-3 (v1.0) march 1, 2005 advance product specification r revision history the following table shows the revision history for this document. the spartan-3e family data sheet ds312-1, spartan-3e fpga family: introduction and ordering information (module 1) ds312-2, spartan-3e fpga family: functional description (module 2) ds312-3, spartan-3e fpga family: dc and switching characteristics (module 3) ds312-4, spartan-3e fpga family: pinout descriptions (module 4) date version revision 03/01/05 1.0 initial xilinx release. ds312-4 (v1.1) march 21, 2005 www.xilinx.com 1 advance product specification ? 2005 xilinx, inc. all rights reserved. xilinx, the xilinx logo, and other designated brands included herein are trademarks of xilinx, inc. all other trademarks are the property of their respective owners. introduction this section describes the various pins on a spartan?-3e fpga and how they connect within the supported compo- nent packages. pin types a majority of the pins on a spartan-3e fpga are gen- eral-purpose, user-defined i/o pins. there are, however, up to 11 different functional types of pins on spartan-3e pack- ages, as outlined in ta b l e 1 . in the package footprint draw- ings that follow, the individual pins are color-coded according to pin type as in the table. 072 spartan-3e fpga family: pinout descriptions ds312-4 (v1.1) march 21, 2005 00 advance product specification r table 1: types of pins on spartan-3e fpgas type / color code description pin name(s) in type i/o unrestricted, general-purpose user-i/o pin. most pins can be paired together to form differential i/os. io io_lxxy_# input unrestricted, general-purpose input-only pin. this pin does not have an output structure. ip ip_lxxy_# dual dual-purpose pin used in some configuration modes during the configuration process and then usually available as a user i/o after configuration. if the pin is not used during configuration, this pin behaves as an i/o-type pin. some of the dual-purpose pins are also global or edge clock inputs (gclk). m[2:0] hswap cclk mosi/csi_b d[7:1] d0/din cso_b rdwr_b busy/dout init_b a[23:20] a19/vs2 a18/vs1 a17/vs0 a[16:0] ldc[2:0] hdc vref dual-purpose pin that is either a user-i/o pin or, along with all other vref pins in the same bank, provides a reference voltage input for certain i/o standards. if used for a reference voltage within a bank, all vref pins within the bank must be connected. ip/vref_# ip_lxx_#/vref_# gclk lhclk rhclk either a user-i/o pin or an input to a specific clock buffer driver. every package has 16 global clock inputs that optionally clock the entire device. the rhclk inputs optionally clock the right-hand side of the device. the lhclk inputs optionally clock the left-hand side of the device. some of the clock pins are shared with the dual-purpose configuration pins and are considered dual-type. gclk[15:0], lhclk[7:0], rhclk[7:0] config dedicated configuration pin. not available as a user-i/o pin. every package has two dedicated configuration pins. these pins are powered by vccaux. done, prog_b pinout descriptions 2 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r i/os with lxxy_# are part of a differential output pair. ?l? indi- cates differential output capability. the ?xx? field is a two-digit integer, unique to each bank that identifies a differ- ential pin-pair. the ?y? field is either ?p? for the true signal or ?n? for the inverted signal in the differential pair. the ?#? field is the i/o bank number. differential pair labeling a pin supports differential standards if the pin is labeled in the format ?lxxy_#?. the pin name suffix has the following significance. figure 1 provides a specific example showing a differential input to and a differential output from bank 1. ?l? indicates that the pin is part of a differentia l pair. "xx" is a two-digit integer, unique for each bank, that identifies a differential pin-pair. ?y? is replaced by ?p? for the true signal or ?n? for the inverted. these two pins form one differential pin-pair. ?#? is an integer, 0 through 3, indicating the associated i/o bank. jtag dedicated jtag pin. not available as a user-i/o pin. every package has four dedicated jtag pins. these pins are powered by vccaux. tdi, tms, tck, tdo gnd dedicated ground pin. the number of gnd pins depends on the package used. all must be connected. gnd vccaux dedicated auxiliary power supply pin. the number of vccaux pins depends on the package used. all must be connected to +2.5v. vccaux vccint dedicated internal core logic power supply pin. the number of vccint pins depends on the package used. all must be connected to +1.2v. vccint vcco along with all the other vcco pins in the same bank, this pin supplies power to the output buffers within the i/o bank and sets the input threshold voltage for some i/o standards. vcco_# n.c. this package pin is not connected in this specific device/package combination but may be connected in larger devices in the same package. n.c. notes: 1. # = i/o bank number, an integer between 0 and 3. table 1: types of pins on spartan-3e fpgas type / color code description pin name(s) in type figure 1: differential pair labeling io_l38p_1 io_l38n_1 io_l39p_1 io_l39n_1 bank 2 bank 1 pair number bank number positive polarity, true driver negative polarity, inverted driver bank 3 bank 0 spartan-3e fpga ds312-4_00_022305 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 3 advance product specification r package overview ta b l e 2 shows the eight low-cost, space-saving production package styles for the spartan-3e family. each package style is available as a standard and an environmen- tally-friendly lead-free (pb-free) option. the pb-free pack- ages include an extra ?g? in the package style name. for example, the standard "vq100" package becomes "vqg100" when ordered as the pb-free option. the mechanical dimensions of the standard and pb-free pack- ages are similar, as shown in the mechanical drawings pro- vided in ta b l e 4 . not all spartan-3e densities are available in all packages. for a specific package, however, there is a common foot- print that supports all the devices available in that package. see the footprint diagrams that follow. selecting the right package option spartan-3 fpgas are available in both quad-flat pack (qfp) and ball grid array (bga) packaging options. while qfp packaging offers the lowest absolute cost, the bga packages are superior in almost every other aspect, as summarized in ta bl e 3 . consequently, xilinx recommends using bga packaging whenever possible. table 2: spartan-3e family package options package leads type maximum i/o pitch (mm) area (mm) height (mm) vq100 / vqg100 100 very-thin quad flat pack (vqfp) 66 0.5 16 x 16 1.20 cp132 / cpg132 132 chip-scale package (csp) 92 0.5 8 x 8 1.10 tq144 / tqg144 144 thin quad flat pack (tqfp) 108 0.5 22 x 22 1.60 pq208 / pqg208 208 plastic quad flat pack (pqfp) 158 0.5 30.6 x 30.6 4.10 ft256 / ftg256 256 fine-pitch, thin ball grid array (fbga) 190 1.0 17 x 17 1.55 fg320 / fgg320 320 fine-pitch ball grid array (fbga) 250 1.0 19 x 19 2.00 fg400 / fgg400 400 fine-pitch ball grid array (fbga) 304 1.0 21 x 21 2.60 fg484 / fgg484 484 fine-pitch ball grid array (fbga) 376 1.0 23 x 23 2.60 table 3: qfp and bga comparison characteristic quad flat pack (qfp) ball grid array (bga) maximum user i/o 158 376 packing density (logic/area) good better signal integrity fair better simultaneous switching output (sso) support limited better thermal dissipation fair better minimum printed circuit board (pcb) layers 4 6 hand assembly/rework possible difficult pinout descriptions 4 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r mechanical drawings detailed mechanical drawings for each package type are available from the xilinx website at the specified location in ta b l e 4 . package pins by type each package has three separate voltage supply inputs?vccint, vccaux, and vcco?and a common ground return, gnd. the numbers of pins dedicated to these functions vary by package, as shown in ta bl e 5 . a majority of package pins are user-defined i/o or input pins. however, the numbers and characteristics of these i/o depend on the device type and the package in which it is available, as shown in ta b l e 6 . the table shows the maxi- mum number of single-ended i/o pins available, assuming that all i/o-, input-, dual-, vref-, and gclk-type pins are used as general-purpose i/o. likewise, the table shows the maximum number of differential pin-pairs available on the package. finally, the table shows how the total maxi- mum user-i/os are distributed by pin type, including the number of unconnected?i.e., n.c.?pins on the device. table 4: xilinx package mechanical drawings package web link (url) vq100 / vqg100 http://www.xilinx.com/bvdocs/packages/vq100.pdf cp132 / cpg132 http://www.xilinx.com/bvdocs/packages/cp132.pdf tq144 / tqg144 http://www.xilinx.com/bvdocs/packages/tq144.pdf pq208 / pqg208 http://www.xilinx.com/bvdocs/packages/pq208.pdf ft256 / ftg256 http://www.xilinx.com/bvdocs/packages/ft256.pdf fg320 / fgg320 http://www.xilinx.com/bvdocs/packages/fg320.pdf fg400 / fgg400 http://www.xilinx.com/bvdocs/packages/fg400.pdf fg484 / fgg484 http://www.xilinx.com/bvdocs/packages/fg484.pdf table 5: power and ground supply pins by package package vccint vccaux vcco gnd vq100 4 4 8 12 cp132 6 4 8 16 tq144 4 4 9 13 pq208 4 8 12 20 ft256 8 8 16 28 fg320 8 8 20 28 fg400 16 8 24 42 fg484 16 10 28 48 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 5 advance product specification r electronic versions of the package pinout tables and foot- prints are available for download from the xilinx web site. download the files from the following location: using a spreadsheet program, the data can be sorted and reformat- ted according to any specific needs. similarly, the ascii-text file is easily parsed by most scripting programs. http://www.xilinx.com/bvdocs/publications/s3e_pin.zip table 6: maximum user i/o by package device package maximum user i/os maximum differential pairs all possible i/os by type i/o input dual vref gclk n.c. XC3S100E vq100 66 30 16 1 21 4 24 0 xc3s250e 66 30 16 1 21 4 24 0 xc3s250e cp132 92 41 22 0 46 8 16 0 xc3s500e 92 41 22 0 46 8 16 0 XC3S100E tq144 108 40 22 19 42 9 16 0 xc3s250e 108 40 20 21 42 9 16 0 xc3s250e pq208 158 65 58 25 46 13 16 0 xc3s500e 158 65 58 25 46 13 16 0 xc3s250e ft256 172 68 62 33 46 15 16 16 xc3s500e 190 77 76 33 46 19 16 0 xc3s1200e 190 77 78 31 46 19 16 0 xc3s500e fg320 232 92 102 48 46 20 16 18 xc3s1200e 250 99 120 47 46 21 16 0 xc3s1600e 250 99 119 48 46 21 16 0 xc3s1200e fg400 304 124 156 62 46 24 16 0 xc3s1600e 304 124 156 62 46 24 16 0 xc3s1600e fg484 376 156 214 72 46 28 16 0 pinout descriptions 6 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r vq100: 100-lead very-thin quad flat package the XC3S100E and the xc3s250e devices are available in the 100-lead very-thin quad flat package, vq100. both devices share a common footprint for this package as shown in ta bl e 7 and figure 2 . ta b l e 7 lists all the package pins. they are sorted by bank number and then by pin name of the largest device. pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. the vq100 package does not support the byte-wide peripheral interface (bpi) configuration mode. conse- quently, the vq100 footprint has fewer dual-type pins than other packages. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip . pinout table ta b l e 7 shows the pinout for production spartan-3e fpgas in the vq100 package. the xc3s100 engineering samples have a slightly different pinout, as described in ta b l e 9 . table 7: vq100 package pinout bank XC3S100E xc3s250e pin name vq100 pin number type 0 io p92 i/o 0 io_l01n_0 p79 i/o 0 io_l01p_0 p78 i/o 0 io_l02n_0/gclk5 p84 gclk 0 io_l02p_0/gclk4 p83 gclk 0 io_l03n_0/gclk7 p86 gclk 0 io_l03p_0/gclk6 p85 gclk 0 io_l05n_0/gclk11 p91 gclk 0 io_l05p_0/gclk10 p90 gclk 0 io_l06n_0/vref_0 p95 vref 0 io_l06p_0 p94 i/o 0 io_l07n_0/hswap p99 dual 0 io_l07p_0 p98 i/o 0 ip_l04n_0/gclk9 p89 gclk 0 ip_l04p_0/gclk8 p88 gclk 0 vcco_0 p82 vcco 0 vcco_0 p97 vcco 1 io_l01n_1 p54 i/o 1 io_l01p_1 p53 i/o 1 io_l02n_1 p58 i/o 1 io_l02p_1 p57 i/o 1 io_l03n_1/rhclk1 p61 rhclk 1 io_l03p_1/rhclk0 p60 rhclk 1 io_l04n_1/rhclk3 p63 rhclk 1 io_l04p_1/rhclk2 p62 rhclk 1 io_l05n_1/rhclk5 p66 rhclk 1 io_l05p_1/rhclk4 p65 rhclk 1 io_l06n_1/rhclk7 p68 rhclk 1 io_l06p_1/rhclk6 p67 rhclk 1 io_l07n_1 p71 i/o 1 io_l07p_1 p70 i/o 1 ip/vref_1 p69 vref 1 vcco_1 p55 vcco 1 vcco_1 p73 vcco 2 io/d5 p34 dual 2 io/m1 p42 dual 2 io_l01n_2/init_b p25 dual 2 io_l01p_2/cso_b p24 dual 2 io_l02n_2/mosi/csi_b p27 dual 2 io_l02p_2/dout/busy p26 dual 2 io_l03n_2/d6/gclk13 p33 dual/gclk 2 io_l03p_2/d7/gclk12 p32 dual/gclk 2 io_l04n_2/d3/gclk15 p36 dual/gclk 2 io_l04p_2/d4/gclk14 p35 dual/gclk 2 io_l06n_2/d1/gclk3 p41 dual/gclk 2 io_l06p_2/d2/gclk2 p40 dual/gclk 2 io_l07n_2/din/d0 p44 dual 2 io_l07p_2/m0 p43 dual 2 io_l08n_2/vs1 p48 dual 2 io_l08p_2/vs2 p47 dual ta b l e 7 : vq100 package pinout bank XC3S100E xc3s250e pin name vq100 pin number type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 7 advance product specification r 2 io_l09n_2/cclk p50 dual 2 io_l09p_2/vs0 p49 dual 2 ip/vref_2 p30 vref 2 ip_l05n_2/m2/gclk1 p39 dual/gclk 2 ip_l05p_2/rdwr_b/ gclk0 p38 dual/gclk 2 vcco_2 p31 vcco 2 vcco_2 p45 vcco 3 io_l01n_3 p3 i/o 3 io_l01p_3 p2 i/o 3 io_l02n_3/vref_3 p5 vref 3 io_l02p_3 p4 i/o 3 io_l03n_3/lhclk1 p10 lhclk 3 io_l03p_3/lhclk0 p9 lhclk 3 io_l04n_3/lhclk3 p12 lhclk 3 io_l04p_3/lhclk2 p11 lhclk 3 io_l05n_3/lhclk5 p16 lhclk 3 io_l05p_3/lhclk4 p15 lhclk 3 io_l06n_3/lhclk7 p18 lhclk 3 io_l06p_3/lhclk6 p17 lhclk 3 io_l07n_3 p23 i/o 3 io_l07p_3 p22 i/o 3 ip p13 input 3 vcco_3 p8 vcco 3 vcco_3 p20 vcco gnd gnd p7 gnd gnd gnd p14 gnd gnd gnd p19 gnd gnd gnd p29 gnd gnd gnd p37 gnd gnd gnd p52 gnd gnd gnd p59 gnd gnd gnd p64 gnd gnd gnd p72 gnd gnd gnd p81 gnd table 7: vq100 package pinout bank XC3S100E xc3s250e pin name vq100 pin number type gnd gnd p87 gnd gnd gnd p93 gnd vccaux done p51 config vccaux prog_b p1 config vccaux tck p77 jtag vccaux tdi p100 jtag vccaux tdo p76 jtag vccaux tms p75 jtag vccaux vccaux p21 vccaux vccaux vccaux p46 vccaux vccaux vccaux p74 vccaux vccaux vccaux p96 vccaux vccint vccint p6 vccint vccint vccint p28 vccint vccint vccint p56 vccint vccint vccint p80 vccint ta b l e 7 : vq100 package pinout bank XC3S100E xc3s250e pin name vq100 pin number type pinout descriptions 8 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r user i/os by bank ta b l e 8 indicates how the 66 available user-i/o pins are dis- tributed between the four i/o banks on the vq100 package. footprint migration differences the production XC3S100E and xc3s250e fpgas have identical footprints in the vq100 package. designs can migrate between the XC3S100E and xc3s250e without further consideration. the pinout changed slightly between the XC3S100E engi- neering samples and the production devices, as shown in ta b l e 9 . in the engineering samples, the mode select pins m1 and m0 overlap with two global clock inputs feeding the bottom-edge global buffers and dcms. in the production devices, the mode pins are swapped with parallel mode data pins, d1 and d2. this way, these two mode pins do not interfere with global clock inputs. table 8: user i/os per bank for XC3S100E and xc3s250e in the vq100 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 15 5 0 1 1 8 right 1 15 6 0 0 1 8 bottom 2 19 0 0 18 1 0 left 3 17 5 1 2 1 8 total 66 16 1 21 4 24 ta b l e 9 : XC3S100E pinout changes between production devices and engineering samples vq100 pin XC3S100E production devices XC3S100E engineering samples p40 d2/gclk2 m1/gclk2 p41 d1/gclk3 m0/gclk3 p42 m1 d2 p43 m0 d1 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 9 advance product specification r vq100 footprint in figure 2 , note pin 1 indicator in top-left corner and logo orientation. the engineering sample footprint is slightly dif- ferent. figure 2: vq100 package production footprint (top view). engin eering samples have slightly different footprint. tdi io_l07n_0/hswap io_l07p_0 vcco_0 vccaux io_l06n_0/vref_0 io_l06p_0 gnd io io_l05n_0/gclk11 io_l05p_0/gclk10 ip_l04n_0/gclk9 ip_l04p_0/gclk8 gnd io_l03n_0/gclk7 io_l03p_0/gclk6 io_l02n_0/gclk5 io_l02p_0/gclk4 vcco_0 gnd vccint io_l01n_0 io_l01p_0 tck tdo 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 prog_b 1 75 t ms i o _l01p_3 2 74 v cc aux io_l01n_3 3 73 vcco_1 io_l02p_3 4 72 gnd io_l02n_3/vref_3 5 71 io_l07n_1 vccint 6 70 io_l07p_1 gnd 7 69 ip/vref_1 vcco_3 8 68 io_l06n_1/rhclk7 io_l03p_3/lhclk0 9 67 io_l06p_1/rhclk6 io_l03n_3/lhclk1 10 66 io_l05n_1/rhclk5 io_l04p_3/lhclk2 11 65 io_l05p_1/rhclk4 io_l04n_3/lhclk3 12 64 gnd ip 13 63 io_l04n_1/rhclk3 gnd 14 62 io_l04p_1/rhclk2 io_l05p_3/lhclk4 15 61 io_l03n_1/rhclk1 io_l05n_3/lhclk5 16 60 io_l03p_1/rhclk0 io_l06p_3/lhclk6 17 59 gnd io_l06n_3/lhclk7 18 58 io_l02n_1 gnd 19 57 io_l02p_1 vcco_3 20 56 vccint vccaux 21 55 vcco_1 io_l07p_3 22 54 io_l01n_1 io_l07n_3 23 53 io_l01p_1 io_l01p_2/cso_b 24 52 gnd io_l01n_2/init_b 25 51 done 26 27 28 29 30 31 34 37 42 43 44 45 46 47 48 49 50 io_l02p_2/dout/busy io_l02n_2/mosi/csi_b vccint gnd ip/vref_2 vcco_2 io_l03p_2/d7/gclk12 io_l03n_2/d6/gclk13 io/d5 io_l04p_2/d4/gclk14 io_l04n_2/d3/gclk15 gnd ip_l05p_2/rdwr_b/gclk0 ip_l05n_2/m2/gclk1 io_l06p_2/d2/gclk2 io_l06n_2/d1/gclk3 io/m1 io_l07p_2/m0 io_l07n_2/din/d0 vcco_2 vccaux io_l08p_2/vs2 io_l08n_2/vs1 io_l09p_2/vs0 io_l09n_2/cclk bank 0 bank 3 bank 2 bank 1 32 33 35 36 38 39 40 41 ds312-4_02_030705 16 i/o: unrestricted, general-purpose user i/o 21 dual: configuration pin, then possible user-i/o 4 vref: user i/o or input voltage reference for bank 1 input: unrestricted, general-purpose input pin 24 gclk: user i/o, input, or global buffer input 8 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 4 vccint: internal core supply voltage (+1.2v) 0 n.c.: not connected 12 gnd: ground 4 vccaux: auxiliary supply voltage (+2.5v) pinout descriptions 10 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r cp132: 132-ball chip-scale package the xc3s250e and the xc3s500e fpgas are available in the 132-lead chip-scale package, cp132. both devices share a common footprint for this package as shown in ta b l e 1 0 and figure 3 . ta b l e 1 0 lists all the cp132 package pins. they are sorted by bank number and then by pin name. pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. physically, the d14 and k2 balls on the xc3s250e fpga are not connected but should be connected to vccint to maintain density migration compatibility. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web- site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip . pinout table table 10: cp132 package pinout bank xc3s250e xc3s500e pin name cp132 ball type 0 io_l01n_0 c12 i/o 0 io_l01p_0 a13 i/o 0 io_l02n_0 a12 i/o 0 io_l02p_0 b12 i/o 0 io_l03n_0/vref_0 b11 vref 0 io_l03p_0 c11 i/o 0 io_l04n_0/gclk5 c9 gclk 0 io_l04p_0/gclk4 a10 gclk 0 io_l05n_0/gclk7 a9 gclk 0 io_l05p_0/gclk6 b9 gclk 0 io_l07n_0/gclk11 b7 gclk 0 io_l07p_0/gclk10 a7 gclk 0 io_l08n_0/vref_0 c6 vref 0 io_l08p_0 b6 i/o 0 io_l09n_0 c5 i/o 0 io_l09p_0 b5 i/o 0 io_l10n_0 c4 i/o 0 io_l10p_0 b4 i/o 0 io_l11n_0/hswap b3 dual 0 io_l11p_0 a3 i/o 0 ip_l06n_0/gclk9 c8 gclk 0 ip_l06p_0/gclk8 b8 gclk 0 vcco_0 a6 vcco 0 vcco_0 b10 vcco 1io/a0 f12 dual 1 io/vref_1 k13 vref 1 io_l01n_1/a15 n14 dual 1 io_l01p_1/a16 n13 dual 1 io_l02n_1/a13 m13 dual 1 io_l02p_1/a14 m12 dual 1 io_l03n_1/a11 l14 dual 1 io_l03p_1/a12 l13 dual 1 io_l04n_1/a9/rhclk1 j12 rhclk/ dual 1 io_l04p_1/a10/rhclk0 k14 rhclk/ dual 1 io_l05n_1/a7/rhclk3/ trdy1 j14 rhclk/ dual 1 io_l05p_1/a8/rhclk2 j13 rhclk/ dual 1 io_l06n_1/a5/rhclk5 h12 rhclk/ dual 1 io_l06p_1/a6/rhclk4/ irdy1 h13 rhclk/ dual 1 io_l07n_1/a3/rhclk7 g13 rhclk/ dual 1 io_l07p_1/a4/rhclk6 g14 rhclk/ dual 1 io_l08n_1/a1 f13 dual 1 io_l08p_1/a2 f14 dual 1 io_l09n_1/ldc0 d12 dual 1 io_l09p_1/hdc d13 dual 1 io_l10n_1/ldc2 c13 dual 1 io_l10p_1/ldc1 c14 dual 1 ip/vref_1 g12 vref 1 vcco_1 e13 vcco 1 vcco_1 m14 vcco 2 io/d5 p4 dual table 10: cp132 package pinout bank xc3s250e xc3s500e pin name cp132 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 11 advance product specification r 2 io/m1 n7 dual 2 io/vref_2 p11 vref 2 io_l01n_2/init_b n1 dual 2 io_l01p_2/cso_b m2 dual 2 io_l02n_2/mosi/csi_b n2 dual 2 io_l02p_2/dout/busy p1 dual 2 io_l03n_2/d6/gclk13 n4 dual/ gclk 2 io_l03p_2/d7/gclk12 m4 dual/ gclk 2 io_l04n_2/d3/gclk15 n5 dual/ gclk 2 io_l04p_2/d4/gclk14 m5 dual/ gclk 2 io_l06n_2/d1/gclk3 p7 dual/ gclk 2 io_l06p_2/d2/gclk2 p6 dual/ gclk 2 io_l07n_2/din/d0 n8 dual 2 io_l07p_2/m0 p8 dual 2 io_l08n_2/a22 m9 dual 2 io_l08p_2/a23 n9 dual 2 io_l09n_2/a20 m10 dual 2 io_l09p_2/a21 n10 dual 2 io_l10n_2/vs1/a18 m11 dual 2 io_l10p_2/vs2/a19 n11 dual 2 io_l11n_2/cclk n12 dual 2 io_l11p_2/vs0/a17 p12 dual 2 ip/vref_2 n3 vref 2 ip_l05n_2/m2/gclk1 n6 dual/ gclk 2 ip_l05p_2/rdwr_b/ gclk0 m6 dual/ gclk 2 vcco_2 m8 vcco 2 vcco_2 p3 vcco 3io j3 i/o 3 io/vref_3 k3 vref 3 io_l01n_3 b1 i/o table 10: cp132 package pinout bank xc3s250e xc3s500e pin name cp132 ball type 3 io_l01p_3 b2 i/o 3 io_l02n_3 c2 i/o 3 io_l02p_3 c3 i/o 3 io_l03n_3 d1 i/o 3 io_l03p_3 d2 i/o 3 io_l04n_3/lhclk1 f2 lhclk 3 io_l04p_3/lhclk0 f3 lhclk 3 io_l05n_3/lhclk3/irdy2 g1 lhclk 3 io_l05p_3/lhclk2 f1 lhclk 3 io_l06n_3/lhclk5 h1 lhclk 3 io_l06p_3/lhclk4/trdy2 g3 lhclk 3 io_l07n_3/lhclk7 h3 lhclk 3 io_l07p_3/lhclk6 h2 lhclk 3 io_l08n_3 l2 i/o 3 io_l08p_3 l1 i/o 3 io_l09n_3 m1 i/o 3 io_l09p_3 l3 i/o 3 ip/vref_3 e2 vref 3 vcco_3 e1 vcco 3 vcco_3 j2 vcco gnd gnd a4 gnd gnd gnd a8 gnd gnd gnd c1 gnd gnd gnd c7 gnd gnd gnd c10 gnd gnd gnd e3 gnd gnd gnd e14 gnd gnd gnd g2 gnd gnd gnd h14 gnd gnd gnd j1 gnd gnd gnd k12 gnd gnd gnd m3 gnd gnd gnd m7 gnd gnd gnd p5 gnd table 10: cp132 package pinout bank xc3s250e xc3s500e pin name cp132 ball type pinout descriptions 12 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r user i/os by bank ta b l e 2 0 indicates how the 92 available user-i/o pins are distributed between the four i/o banks on the cp132 pack- age. footprint migration differences the production xc3s250e and xc3s500e fpgas have identical footprints in the cp132 package. designs can migrate between the xc3s250e and xc3s500e without further consideration. gnd gnd p10 gnd gnd gnd p14 gnd vccaux done p13 config vccaux prog_b a1 config vccaux tck b13 jtag vccaux tdi a2 jtag vccaux tdo a14 jtag vccaux tms b14 jtag vccaux vccaux a5 vccaux vccaux vccaux e12 vccaux vccaux vccaux k1 vccaux table 10: cp132 package pinout bank xc3s250e xc3s500e pin name cp132 ball type vccaux vccaux p9 vccaux vccint vccint a11 vccint vccint vccint d3 vccint vccint vccint d14 vccint vccint vccint k2 vccint vccint vccint l12 vccint vccint vccint p2 vccint table 10: cp132 package pinout bank xc3s250e xc3s500e pin name cp132 ball type table 11: user i/os per bank for the xc3s250e and xc3s500e in the cp132 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 22 11 0 1 2 8 right 1 23 0 0 21 2 0 bottom 2 26 0 0 24 2 0 left 3 21 11 0 0 2 8 total 92 22 0 46 8 16 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 13 advance product specification r cp132 footprint figure 3: cp132 package footprint (top view) 1234567891011121314 a prog_b tdi tdo tms tck i/o l11p_0 i/o l07p_0 i/o l05n_0 i/o l04p_0 vccint i/o l02n_0 i/o l01p_0 b i/o l01n_3 i/o l01p_3 i/o l11n_0 hswap i/o l10p_0 i/o l09p_0 i/o l08p_0 i/o l07n_0 input input l06p_0 i/o l05p_0 i/o l03n_0 i/o l02p_0 c i/o l02n_3 i/o l02p_3 i/o l10n_0 i/o l09n_0 i/o l08n_0 l06n_0 gclk9 gclk5 gclk6 gclk7 gclk4 gclk10 gclk11 gclk8 i/o l04n_0 i/o l03p_0 i/o l01n_0 i/o l10n_1 i/o l10p_1 d i/o l03n_3 i/o l03p_3 vccint i/o l09n_1 ldc0 ldc1 ldc2 i/o l09p_1 hdc vccint e gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vccaux vccaux vccaux vccaux f i/o l05p_3 i/o l04n_3 i/o l04p_3 lhclk0 lhclk1 lhclk2 lhclk5 lhclk6 lhclk7 i/o a0 i/o l08n_1 a1 i/o l08p_1 a2 g i/o l05n_3 lhclk3 i/o l06p_3 lhclk4 trdy2 irdy2 vref_1 vref_1 vref_2 vref_2 vref_3 vref_3 vref_0 vref_0 h i/o l06n_3 i/o l07p_3 i/o l07n_3 j i/o i/o i/o k vccint i/o i/o l i/o l08p_3 i/o l08n_3 i/o l09p_3 vccint i/o l03p_1 a12 i/o l03n_1 a11 m i/o l09n_3 i/o l01p_2 cso_b i/o l08n_2 a22 i/o l09n_2 a20 i/o l10n_2 vs1 a18 i/o l02p_1 a14 i/o l02n_1 a13 n i/o l01n_2 init_b i/o l02n_2 mosi csi_b i/o m1 i/o l07n_2 din d0 i/o l08p_2 a23 i/o l09p_2 a21 i/o l10p_2 vs2 a19 i/o l11n_2 cclk i/o l01p_1 a16 i/o l01n_1 a15 p i/o l02p_2 dout busy vccint vcco_2 vcco_2 vcco_1 vcco_1 vcco_0 vcco_0 vcco_3 vcco_3 i/o d5 i/o l07p_2 m0 i/o i/o l11p_2 vs0 a17 done bank 2 bank 0 bank 3 bank 1 i/o l07p_1 4 rhclk6 l07n_1 rhclk7 a 3 i/o rhclk5 a 5 l06n_1 i/o rhclk4 a6 l06p_1 i/o a rhclk3 l05n_1 i/o 7 a rhclk2 a 8 l05p_1 rhclk1 a 9 l04n_1 rhclk0 a 10 l04p_1 i/o i/o l06n_2 d1 gclk3 i/o l06p_2 d2 gclk2 l05n_2 m2 gclk1 input input input input input l05p_2 rdwr_b gclk0 i/o l04n_2 d3 gclk15 i/o l03n_2 d6 gclk13 i/o l04p_2 d4 gclk14 i/o l03p_2 d7 gclk12 irdy1 trdy1 ds312-4_07_031105 22 i/o: unrestricted, general-purpose user i/o 42 dual: configuration pin, then possible user i/o 8 vref: user i/o or input voltage reference for bank 0 input: unrestricted, general-purpose input pin 16 gclk: user i/o, input, or global buffer input 8 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 6 vccint: internal core supply voltage (+1.2v) 0 n.c.: not connected 16 gnd: ground 4 vccaux: auxiliary supply voltage (+2.5v) pinout descriptions 14 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r tq144: 144-lead thin quad flat package the XC3S100E and the xc3s250e fpgas are available in the 144-lead thin quad flat package, tq144. both devices share a common footprint for this package as shown in ta b l e 1 2 and figure 4 . ta b l e 1 2 lists all the package pins. they are sorted by bank number and then by pin name of the largest device. pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. the tq144 package only supports 20 address output pins in the byte-wide peripheral interface (bpi) configuration mode. in larger packages, there are 24 bpi address out- puts. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip . pinout table ta b l e 1 2 shows the pinout for production spartan-3e fpgas in the vq100 package. the xc3s100 engineering samples have a slightly different pinout, as described in ta b l e 1 5 . table 12: tq144 package pinout bank XC3S100E pin name xc3s250e pin name tq144 pin type 0 io io p132 i/o 0 io/vref_0 io/vref_0 p124 vref 0 io_l01n_0 io_l01n_0 p113 i/o 0 io_l01p_0 io_l01p_0 p112 i/o 0 io_l02n_0 io_l02n_0 p117 i/o 0 io_l02p_0 io_l02p_0 p116 i/o 0 io_l04n_0/gclk5 io_l04n_0/gclk5 p123 gclk 0 io_l04p_0/gclk4 io_l04p_0/gclk4 p122 gclk 0 io_l05n_0/gclk7 io_l05n_0/gclk7 p126 gclk 0 io_l05p_0/gclk6 io_l05p_0/gclk6 p125 gclk 0 io_l07n_0/gclk11 io_l07n_0/gclk11 p131 gclk 0 io_l07p_0/gclk10 io_l07p_0/gclk10 p130 gclk 0 io_l08n_0/vref_0 io_l08n_0/vref_0 p135 vref 0 io_l08p_0 io_l08p_0 p134 i/o 0 io_l09n_0 io_l09n_0 p140 i/o 0 io_l09p_0 io_l09p_0 p139 i/o 0 io_l10n_0/hswap io_l10n_0/hswap p143 dual 0 io_l10p_0 io_l10p_0 p142 i/o 0 ip ip p111 input 0 ip ip p114 input 0 ip ip p136 input 0 ip ip p141 input 0 ip_l03n_0 ip_l03n_0 p120 input 0 ip_l03p_0 ip_l03p_0 p119 input 0 ip_l06n_0/gclk9 ip_l06n_0/gclk9 p129 gclk 0 ip_l06p_0/gclk8 ip_l06p_0/gclk8 p128 gclk pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 15 advance product specification r 0 vcco_0 vcco_0 p121 vcco 0 vcco_0 vcco_0 p138 vcco 1 io/a0 io/a0 p98 dual 1 io/vref_1 io/vref_1 p83 vref 1 io_l01n_1/a15 io_l01n_1/a15 p75 dual 1 io_l01p_1/a16 io_l01p_1/a16 p74 dual 1 io_l02n_1/a13 io_l02n_1/a13 p77 dual 1 io_l02p_1/a14 io_l02p_1/a14 p76 dual 1 io_l03n_1/a11 io_l03n_1/a11 p82 dual 1 io_l03p_1/a12 io_l03p_1/a12 p81 dual 1 io_l04n_1/a9/rhclk1 io_l04n_1/a9/rhclk1 p86 rhclk/dual 1 io_l04p_1/a10/rhclk0 io_l04p_1/a10/rhclk0 p85 rhclk/dual 1 io_l05n_1/a7/rhclk3/trdy1 io_l05n_1/a7/rhclk3 p88 rhclk/dual 1 io_l05p_1/a8/rhclk2 io_l05p_1/a8/rhclk2 p87 rhclk/dual 1 io_l06n_1/a5/rhclk5 io_l06n_1/a5/rhclk5 p92 rhclk/dual 1 io_l06p_1/a6/rhclk4/irdy1 io_l06p_1/a6/rhclk4 p91 rhclk/dual 1 io_l07n_1/a3/rhclk7 io_l07n_1/a3/rhclk7 p94 rhclk/dual 1 io_l07p_1/a4/rhclk6 io_l07p_1/a4/rhclk6 p93 rhclk/dual 1 io_l08n_1/a1 io_l08n_1/a1 p97 dual 1 io_l08p_1/a2 io_l08p_1/a2 p96 dual 1 io_l09n_1/ldc0 io_l09n_1/ldc0 p104 dual 1 io_l09p_1/hdc io_l09p_1/hdc p103 dual 1 io_l10n_1/ldc2 io_l10n_1/ldc2 p106 dual 1 io_l10p_1/ldc1 io_l10p_1/ldc1 p105 dual 1 ip ip p78 input 1 ip ip p84 input 1 ip ip p89 input 1 ip ip p101 input 1 ip ip p107 input 1 ip/vref_1 ip/vref_1 p95 vref 1 vcco_1 vcco_1 p79 vcco 1 vcco_1 vcco_1 p100 vcco 2 io/d5 io/d5 p52 dual 2 io/m1 io/m1 p60 dual 2 ip/vref_2 io/vref_2 p66 100e: vref(input) 250e: vref(i/o) table 12: tq144 package pinout (continued) bank XC3S100E pin name xc3s250e pin name tq144 pin type pinout descriptions 16 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 2 io_l01n_2/init_b io_l01n_2/init_b p40 dual 2 io_l01p_2/cso_b io_l01p_2/cso_b p39 dual 2 io_l02n_2/mosi/csi_b io_l02n_2/mosi/csi_b p44 dual 2 io_l02p_2/dout/busy io_l02p_2/dout/busy p43 dual 2 io_l04n_2/d6/gclk13 io_l04n_2/d6/gclk13 p51 dual/gclk 2 io_l04p_2/d7/gclk12 io_l04p_2/d7/gclk12 p50 dual/gclk 2 io_l05n_2/d3/gclk15 io_l05n_2/d3/gclk15 p54 dual/gclk 2 io_l05p_2/d4/gclk14 io_l05p_2/d4/gclk14 p53 dual/gclk 2 io_l07n_2/d1/gclk3 io_l07n_2/d1/gclk3 p59 dual/gclk 2 io_l07p_2/d2/gclk2 io_l07p_2/d2/gclk2 p58 dual/gclk 2 io_l08n_2/din/d0 io_l08n_2/din/d0 p63 dual 2 io_l08p_2/m0 io_l08p_2/m0 p62 dual 2 io_l09n_2/vs1/a18 io_l09n_2/vs1/a18 p68 dual 2 io_l09p_2/vs2/a19 io_l09p_2/vs2/a19 p67 dual 2 io_l10n_2/cclk io_l10n_2/cclk p71 dual 2 io_l10p_2/vs0/a17 io_l10p_2/vs0/a17 p70 dual 2 ip ip p38 input 2 ip ip p41 input 2 ip ip p69 input 2 ip_l03n_2/vref_2 ip_l03n_2/vref_2 p48 vref 2 ip_l03p_2 ip_l03p_2 p47 input 2 ip_l06n_2/m2/gclk1 ip_l06n_2/m2/gclk1 p57 dual/gclk 2 ip_l06p_2/rdwr_b/gclk0 ip_l06p_2/rdwr_b/gclk0 p56 dual/gclk 2 vcco_2 vcco_2 p42 vcco 2 vcco_2 vcco_2 p49 vcco 2 vcco_2 vcco_2 p64 vcco 3 ip/vref_3 io/vref_3 p31 100e: vref(input) 250e: vref(i/o) 3 io_l01n_3 io_l01n_3 p3 i/o 3 io_l01p_3 io_l01p_3 p2 i/o 3 io_l02n_3/vref_3 io_l02n_3/vref_3 p5 vref 3 io_l02p_3 io_l02p_3 p4 i/o 3 io_l03n_3 io_l03n_3 p8 i/o 3 io_l03p_3 io_l03p_3 p7 i/o 3 io_l04n_3/lhclk1 io_l04n_3/lhclk1 p15 lhclk 3 io_l04p_3/lhclk0 io_l04p_3/lhclk0 p14 lhclk table 12: tq144 package pinout (continued) bank XC3S100E pin name xc3s250e pin name tq144 pin type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 17 advance product specification r 3 io_l05n_3/lhclk3/irdy2 io_l05n_3/lhclk3 p17 lhclk 3 io_l05p_3/lhclk2 io_l05p_3/lhclk2 p16 lhclk 3 io_l06n_3/lhclk5 io_l06n_3/lhclk5 p21 lhclk 3 io_l06p_3/lhclk4/trdy2 io_l06p_3/lhclk4 p20 lhclk 3 io_l07n_3/lhclk7 io_l07n_3/lhclk7 p23 lhclk 3 io_l07p_3/lhclk6 io_l07p_3/lhclk6 p22 lhclk 3 io_l08n_3 io_l08n_3 p26 i/o 3 io_l08p_3 io_l08p_3 p25 i/o 3 io_l09n_3 io_l09n_3 p33 i/o 3 io_l09p_3 io_l09p_3 p32 i/o 3 io_l10n_3 io_l10n_3 p35 i/o 3 io_l10p_3 io_l10p_3 p34 i/o 3 ip ip p6 input 3 io ip p10 100e: i/o 250e: input 3 ip ip p18 input 3 ip ip p24 input 3 io ip p29 100e: i/o 250e: input 3 ip ip p36 input 3 ip/vref_3 ip/vref_3 p12 vref 3 vcco_3 vcco_3 p13 vcco 3 vcco_3 vcco_3 p28 vcco gnd gnd gnd p11 gnd gnd gnd gnd p19 gnd gnd gnd gnd p27 gnd gnd gnd gnd p37 gnd gnd gnd gnd p46 gnd gnd gnd gnd p55 gnd gnd gnd gnd p61 gnd gnd gnd gnd p73 gnd gnd gnd gnd p90 gnd gnd gnd gnd p99 gnd gnd gnd gnd p118 gnd gnd gnd gnd p127 gnd gnd gnd gnd p133 gnd table 12: tq144 package pinout (continued) bank XC3S100E pin name xc3s250e pin name tq144 pin type pinout descriptions 18 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r user i/os by bank ta b l e 1 3 and ta b l e 1 4 indicate how the 108 available user-i/o pins are distributed between the four i/o banks on the tq144 package. vccaux done done p72 config vccaux prog_b prog_b p1 config vccaux tck tck p110 jtag vccaux tdi tdi p144 jtag vccaux tdo tdo p109 jtag vccaux tms tms p108 jtag vccaux vccaux vccaux p30 vccaux vccaux vccaux vccaux p65 vccaux vccaux vccaux vccaux p102 vccaux vccaux vccaux vccaux p137 vccaux vccint vccint vccint p9 vccint vccint vccint vccint p45 vccint vccint vccint vccint p80 vccint vccint vccint vccint p115 vccint table 12: tq144 package pinout (continued) bank XC3S100E pin name xc3s250e pin name tq144 pin type table 13: user i/os per bank for the XC3S100E in the tq144 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 26 9 6 1 2 8 right 1 28 0 5 21 2 0 bottom 2 26 0 4 20 2 0 left 3 28 13 4 0 3 8 total 108 22 19 42 9 16 table 14: user i/os per bank for the xc3s250e in tq144 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 26 9 6 1 2 8 right 1 28 0 5 21 2 0 bottom 2 26 0 4 20 2 0 left 3 28 11 6 0 3 8 total 108 20 21 42 9 16 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 19 advance product specification r footprint migration differences ta b l e 1 5 summarizes any footprint and functionality differ- ences between the XC3S100E and the xc3s250e fpgas that may affect easy migration between devices. there are four such pins. all other pins not listed in ta b l e 1 5 uncondi- tionally migrate between spartan-3e devices available in the tq144 package. the arrows indicate the direction for easy migration. for example, a left-facing arrow indicates that the pin on the xc3s250e unconditionally migrates to the pin on the XC3S100E. it may be possible to migrate the opposite direction depending on the i/o configuration. for example, an i/o pin (type = i/o) can migrate to an input-only pin (type = input) if the i/o pin is configured as an input. the pinout changed slightly between the XC3S100E engi- neering samples and the production devices, as shown in ta b l e 1 6 . in the engineering samples, the mode select pins m1 and m0 overlap with two global clock inputs feeding the bottom edge global buffers and dcms. in the production devices, the mode pins are swapped with parallel mode data pins, d1 and d2. this way, these two mode pins do not interfere with global clock inputs. table 15: tq144 footprint migration differences tq144 pin bank XC3S100E type migration xc3s250e type p10 3 i/o input p29 3 i/o input p31 3 vref(input) vref(i/o) p66 2 vref(input) vref(i/o) differences 4 legend: this pin can unconditionally migrate from the device on the left to the device on the right. migration in the other direction m ay be possible depending on how the pin is configured for the device on the right. this pin can unconditionally migrate from the device on the right to the device on the left. migration in the other direction m ay be possible depending on how the pin is configured for the device on the left. table 16: XC3S100E pinout changes between production devices and engineering samples tq144 pin XC3S100E production devices XC3S100E engineering samples p58 d2/gclk2 m1/gclk2 p59 d1/gclk3 m0/gclk3 p60 m1 d2 p62 m0 d1 pinout descriptions 20 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r tq144 footprint note pin 1 indicator in top-left corner and logo orientation. double arrows ( ) indicates a pinout migration difference between the XC3S100E and xc3s250e. engineering sam- ple footprint is slightly different. figure 4: tq144 package production footprint (top view) tdi io_l10n_0/hswap io_l10p_0 ip io_l09n_0 io_l09p_0 vcco_0 vccaux ip io_l08n_0/vref_0 io_l08p_0 gnd io io_l07n_0/gclk11 io_l07p_0/gclk10 ip_l06n_0/gclk9 ip_l06p_0/gclk8 gnd io_l05n_0/gclk7 io_l05p_0/gclk6 io/vref_0 io_l04n_0/gclk5 io_l04p_0/gclk4 vcco_0 ip_l03n_0 ip_l03p_0 gnd io_l02n_0 io_l02p_0 vccint ip io_l01n_0 io_l01p_0 ip tck tdo 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 prog_b 1 108 tms io_l01p_3 2 107 ip io_l01n_3 3 106 io_l10n_1/ldc2 io_l02p_3 4 105 io_l10p_1/ldc1 io_l02n_3/vref_3 5 104 io_l09n_1/ldc0 ip 6 103 io_l09p_1/hdc io_l03p_3 7 102 vccaux io_l03n_3 8 101 ip vccint 9 100 vcco_1 ( )ip 10 99 gnd gnd 11 98 io/a0 ip/vref_3 12 97 io_l08n_1/a1 vcco_3 13 96 io_l08p_1/a2 io_l04p_3/lhclk0 14 95 ip/vref_1 io_l04n_3/lhclk1 15 io_l07n_1/a3/rhclk7 io_l05p_3/lhclk2 16 io_l07p_1/a4/rhclk6 io_l05n_3/lhclk3 17 io_l06n_1/a5/rhclk5 ip 18 io_l06p_1/a6/rhclk4 gnd 19 90 gnd io_l06p_3/lhclk4 20 89 ip io_l06n_3/lhclk5 21 io_l05n_1/a7/rhclk3 io_l07p_3/lhclk6 22 io_l05p_1/a8/rhclk2 io_l07n_3/lhclk7 23 io_l04n_1/a9/rhclk1 ip 24 io_l04p_1/a10/rhclk0 io_l08p_3 25 84 ip io_l08n_3 26 83 io/vref_1 gnd 27 82 io_l03n_1/a11 vcco_3 28 81 io_l03p_1/a12 ( )ip 29 80 vccint vccaux 30 79 vcco_1 ( ) io/vref_3 31 78 ip io_l09p_3 32 77 io_l02n_1/a13 io_l09n_3 33 76 io_l02p_1/a14 io_l10p_3 34 75 io_l01n_1/a15 io_l10n_3 35 74 io_l01p_1/a16 ip 36 73 gnd 37 38 39 40 41 42 43 44 45 46 47 48 49 52 55 60 61 62 63 64 65 66 67 68 69 70 71 72 gnd ip io_l01p_2/cso_b io_l01n_2/init_b ip vcco_2 io_l02p_2/dout/busy io_l02n_2/mosi/csi_b vccint gnd ip_l03p_2 ip_l03n_2/vref_2 vcco_2 io_l04p_2/d7/gclk12 io_l04n_2/d6/gclk13 io/d5 io_l05p_2/d4/gclk14 io_l05n_2/d3/gclk15 gnd ip_l06p_2/rdwr_b/gclk0 ip_l06n_2/m2/gclk1 io_l07p_2/d2/gclk2 io_l07n_2/d1/gclk3 io/m1 gnd io_l08p_2/m0 io_l08n_2/din/d0 vcco_2 vccaux ( ) io/vref_2 io_l09p_2/vs2/a19 io_l09n_2/vs1/a18 ip io_l10p_2/vs0/a17 io_l10n_2/cclk done bank 0 bank 3 bank 1 bank 2 50 51 53 54 56 57 58 59 85 86 87 88 91 92 93 94 ds312-4_01_030705 20 i/o: unrestricted, general-purpose user i/o 42 dual: configuration pin, then possible user i/o 9 vref: user i/o or input voltage reference for bank 21 input: unrestricted, general-purpose input pin 16 gclk: user i/o, input, or global buffer input 9 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 4 vccint: internal core supply voltage (+1.2v) 0 n.c.: not connected 13 gnd: ground 4 vccaux: auxiliary supply voltage (+2.5v) pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 21 advance product specification r pq208: 208-pin plastic quad flat package the 208-pin plastic quad flat package, pq208, supports two different spartan-3e fpgas, including the xc3s250e and the xc3s500e. ta b l e 1 7 lists all the pq208 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web- site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip . pinout table table 17: pq208 package pinout bank xc3s250e xc3s500e pin name pq208 pin type 0 io p187 i/o 0 io/vref_0 p179 vref 0 io_l01n_0 p161 i/o 0 io_l01p_0 p160 i/o 0 io_l02n_0/vref_0 p163 vref 0 io_l02p_0 p162 i/o 0 io_l03n_0 p165 i/o 0 io_l03p_0 p164 i/o 0 io_l04n_0/vref_0 p168 vref 0 io_l04p_0 p167 i/o 0 io_l05n_0 p172 i/o 0 io_l05p_0 p171 i/o 0 io_l07n_0/gclk5 p178 gclk 0 io_l07p_0/gclk4 p177 gclk 0 io_l08n_0/gclk7 p181 gclk 0 io_l08p_0/gclk6 p180 gclk 0 io_l10n_0/gclk11 p186 gclk 0 io_l10p_0/gclk10 p185 gclk 0 io_l11n_0 p190 i/o 0 io_l11p_0 p189 i/o 0 io_l12n_0/vref_0 p193 vref 0 io_l12p_0 p192 i/o 0 io_l13n_0 p197 i/o 0 io_l13p_0 p196 i/o 0 io_l14n_0/vref_0 p200 vref 0 io_l14p_0 p199 i/o 0 io_l15n_0 p203 i/o 0 io_l15p_0 p202 i/o 0 io_l16n_0/hswap p206 dual 0 io_l16p_0 p205 i/o 0 ip p159 input 0 ip p169 input 0 ip p194 input 0 ip p204 input 0 ip_l06n_0 p175 input 0 ip_l06p_0 p174 input 0 ip_l09n_0/gclk9 p184 gclk 0 ip_l09p_0/gclk8 p183 gclk 0 vcco_0 p176 vcco 0 vcco_0 p191 vcco 0 vcco_0 p201 vcco 1 io_l01n_1/a15 p107 dual 1 io_l01p_1/a16 p106 dual 1 io_l02n_1/a13 p109 dual 1 io_l02p_1/a14 p108 dual 1 io_l03n_1/vref_1 p113 vref 1 io_l03p_1 p112 i/o 1 io_l04n_1 p116 i/o 1 io_l04p_1 p115 i/o 1 io_l05n_1/a11 p120 dual 1 io_l05p_1/a12 p119 dual 1 io_l06n_1/vref_1 p123 vref 1 io_l06p_1 p122 i/o 1 io_l07n_1/a9/rhclk1 p127 rhclk/dual 1 io_l07p_1/a10/rhclk0 p126 rhclk/dual 1 io_l08n_1/a7/rhclk3 p129 rhclk/dual 1 io_l08p_1/a8/rhclk2 p128 rhclk/dual table 17: pq208 package pinout bank xc3s250e xc3s500e pin name pq208 pin type pinout descriptions 22 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 1 io_l09n_1/a5/rhclk5 p133 rhclk/dual 1 io_l09p_1/a6/rhclk4 p132 rhclk/dual 1 io_l10n_1/a3/rhclk7 p135 rhclk/dual 1 io_l10p_1/a4/rhclk6 p134 rhclk/dual 1 io_l11n_1/a1 p138 dual 1 io_l11p_1/a2 p137 dual 1 io_l12n_1/a0 p140 dual 1 io_l12p_1 p139 i/o 1 io_l13n_1 p145 i/o 1 io_l13p_1 p144 i/o 1 io_l14n_1 p147 i/o 1 io_l14p_1 p146 i/o 1 io_l15n_1/ldc0 p151 dual 1 io_l15p_1/hdc p150 dual 1 io_l16n_1/ldc2 p153 dual 1 io_l16p_1/ldc1 p152 dual 1 ip p110 input 1 ip p118 input 1 ip p124 input 1 ip p130 input 1 ip p142 input 1 ip p148 input 1 ip p154 input 1 ip/vref_1 p136 vref 1 vcco_1 p114 vcco 1 vcco_1 p125 vcco 1 vcco_1 p143 vcco 2 io/d5 p76 dual 2 io/m1 p84 dual 2 io/vref_2 p98 vref 2 io_l01n_2/init_b p56 dual 2 io_l01p_2/cso_b p55 dual 2 io_l03n_2/mosi/csi_b p61 dual 2 io_l03p_2/dout/busy p60 dual table 17: pq208 package pinout bank xc3s250e xc3s500e pin name pq208 pin type 2 io_l04n_2 p63 i/o 2 io_l04p_2 p62 i/o 2 io_l05n_2 p65 i/o 2 io_l05p_2 p64 i/o 2 io_l06n_2 p69 i/o 2 io_l06p_2 p68 i/o 2 io_l08n_2/d6/gclk13 p75 dual/gclk 2 io_l08p_2/d7/gclk12 p74 dual/gclk 2 io_l09n_2/d3/gclk15 p78 dual/gclk 2 io_l09p_2/d4/gclk14 p77 dual/gclk 2 io_l11n_2/d1/gclk3 p83 dual/gclk 2 io_l11p_2/d2/gclk2 p82 dual/gclk 2 io_l12n_2/din/d0 p87 dual 2 io_l12p_2/m0 p86 dual 2 io_l13n_2 p90 i/o 2 io_l13p_2 p89 i/o 2 io_l14n_2/a22 p94 dual 2 io_l14p_2/a23 p93 dual 2 io_l15n_2/a20 p97 dual 2 io_l15p_2/a21 p96 dual 2 io_l16n_2/vs1/a18 p100 dual 2 io_l16p_2/vs2/a19 p99 dual 2 io_l17n_2/cclk p103 dual 2 io_l17p_2/vs0/a17 p102 dual 2 ip p54 input 2 ip p91 input 2 ip p101 input 2 ip_l02n_2 p58 input 2 ip_l02p_2 p57 input 2 ip_l07n_2/vref_2 p72 vref 2 ip_l07p_2 p71 input 2 ip_l10n_2/m2/gclk1 p81 dual/gclk 2 ip_l10p_2/rdwr_b/ gclk0 p80 dual/gclk 2 vcco_2 p59 vcco table 17: pq208 package pinout bank xc3s250e xc3s500e pin name pq208 pin type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 23 advance product specification r 2 vcco_2 p73 vcco 2 vcco_2 p88 vcco 3 io/vref_3 p45 vref 3 io_l01n_3 p3 i/o 3 io_l01p_3 p2 i/o 3 io_l02n_3/vref_3 p5 vref 3 io_l02p_3 p4 i/o 3 io_l03n_3 p9 i/o 3 io_l03p_3 p8 i/o 3 io_l04n_3 p12 i/o 3 io_l04p_3 p11 i/o 3 io_l05n_3 p16 i/o 3 io_l05p_3 p15 i/o 3 io_l06n_3 p19 i/o 3 io_l06p_3 p18 i/o 3 io_l07n_3/lhclk1 p23 lhclk 3 io_l07p_3/lhclk0 p22 lhclk 3 io_l08n_3/lhclk3 p25 lhclk 3 io_l08p_3/lhclk2 p24 lhclk 3 io_l09n_3/lhclk5 p29 lhclk 3 io_l09p_3/lhclk4 p28 lhclk 3 io_l10n_3/lhclk7 p31 lhclk 3 io_l10p_3/lhclk6 p30 lhclk 3 io_l11n_3 p34 i/o 3 io_l11p_3 p33 i/o 3 io_l12n_3 p36 i/o 3 io_l12p_3 p35 i/o 3 io_l13n_3 p40 i/o 3 io_l13p_3 p39 i/o 3 io_l14n_3 p42 i/o 3 io_l14p_3 p41 i/o 3 io_l15n_3 p48 i/o 3 io_l15p_3 p47 i/o 3 io_l16n_3 p50 i/o table 17: pq208 package pinout bank xc3s250e xc3s500e pin name pq208 pin type 3 io_l16p_3 p49 i/o 3 ip p6 input 3 ip p14 input 3 ip p26 input 3 ip p32 input 3 ip p43 input 3 ip p51 input 3 ip/vref_3 p20 vref 3 vcco_3 p21 vcco 3 vcco_3 p38 vcco 3 vcco_3 p46 vcco gnd gnd p10 gnd gnd gnd p17 gnd gnd gnd p27 gnd gnd gnd p37 gnd gnd gnd p52 gnd gnd gnd p53 gnd gnd gnd p70 gnd gnd gnd p79 gnd gnd gnd p85 gnd gnd gnd p95 gnd gnd gnd p105 gnd gnd gnd p121 gnd gnd gnd p131 gnd gnd gnd p141 gnd gnd gnd p156 gnd gnd gnd p173 gnd gnd gnd p182 gnd gnd gnd p188 gnd gnd gnd p198 gnd gnd gnd p208 gnd vccaux done p104 config vccaux prog_b p1 config vccaux tck p158 jtag table 17: pq208 package pinout bank xc3s250e xc3s500e pin name pq208 pin type pinout descriptions 24 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r user i/os by bank ta b l e 1 8 indicates how the 158 available user-i/o pins are distributed between the four i/o banks on the pq208 pack- age. footprint migration differences the xc3s250e and xc3s500e fpgas have identical foot- prints in the pq208 package. designs can migrate between the xc3s250e and xc3s500e without further consider- ation. vccaux tdi p207 jtag vccaux tdo p157 jtag vccaux tms p155 jtag vccaux vccaux p7 vccaux vccaux vccaux p44 vccaux vccaux vccaux p66 vccaux vccaux vccaux p92 vccaux vccaux vccaux p111 vccaux vccaux vccaux p149 vccaux vccaux vccaux p166 vccaux vccaux vccaux p195 vccaux vccint vccint p13 vccint table 17: pq208 package pinout bank xc3s250e xc3s500e pin name pq208 pin type vccint vccint p67 vccint vccint vccint p117 vccint vccint vccint p170 vccint table 17: pq208 package pinout bank xc3s250e xc3s500e pin name pq208 pin type table 18: user i/os per bank for the xc3s250e and xc3s500e in the pq208 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 38 18 6 1 5 8 right 1 40 9 7 21 3 0 bottom 2 40 8 6 24 2 0 left 3 40 23 6 0 3 8 total 158 58 25 46 13 16 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 25 advance product specification r pq208 footprint (left) figure 5: pq208 footprint (left) gnd tdi io_l16n_0/hswap io_l16p_0 ip io_l15n_0 io_l15p_0 vcco_0 io_l14n_0/vref_0 io_l14p_0 gnd io_l13n_0 io_l13p_0 vccaux ip io_l12n_0/vref_0 io_l12p_0 vcco_0 io_l11n_0 io_l11p_0 gnd io io_l10n_0/gclk11 io_l10p_0/gclk10 ip_l09n_0/gclk9 ip_l09p_0/gclk8 gnd 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 prog_b 1 io _ l 01 p _3 2 io_l01n_3 3 io_l02p_3 4 io_l02n_3/vref_3 5 ip 6 vccaux 7 io_l03p_3 8 io_l03n_3 9 gnd 10 io_l04p_3 11 io_l04n_3 12 vccint 13 ip 14 io_l05p_3 15 io_l05n_3 16 gnd 17 io_l06p_3 18 io_l06n_3 19 ip/vref_3 20 vcco_3 21 io_l07p_3/lhclk0 22 io_l07n_3/lhclk1 23 io_l08p_3/lhclk2 24 io_l08n_3/lhclk3 25 ip 26 gnd 27 io_l09p_3/lhclk4 28 io_l09n_3/lhclk5 29 io_l10p_3/lhclk6 30 io_l10n_3/lhclk7 31 ip 32 io_l11p_3 33 io_l11n_3 34 io_l12p_3 35 io_l12n_3 36 gnd 37 vcco_3 38 io_l13p_3 39 io_l13n_3 40 io_l14p_3 41 io_l14n_3 42 ip 43 vccaux 44 io/vref_3 45 vcco_3 46 io_l15p_3 47 io_l15n_3 48 io_l16p_3 49 io_l16n_3 50 ip 51 gnd 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 76 79 gnd ip io_l01p_2/cso_b io_l01n_2/init_b ip_l02p_2 ip_l02n_2 vcco_2 io_l03p_2/dout/busy io_l03n_2/mosi/csi_b io_l04p_2 io_l04n_2 io_l05p_2 io_l05n_2 vccaux vccint io_l06p_2 io_l06n_2 gnd ip_l07p_2 ip_l07n_2/vref_2 vcco_2 io_l08p_2/d7/gclk12 io_l08n_2/d6/gclk13 io/d5 io_l09p_2/d4/gclk14 io_l09n_2/d3/gclk15 gnd bank 0 bank 3 bank 2 74 75 77 78 ds312-4_03_030705 pinout descriptions 26 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r pq208 footprint (right) figure 6: pq208 footprint (right) io_l08n_0/gclk7 io_l08p_0/gclk6 io/vref_0 io_l07n_0/gclk5 io_l07p_0/gclk4 vcco_0 ip_l06n_0 ip_l06p_0 gnd io_l05n_0 io_l05p_0 vccint ip io_l04n_0/vref_0 io_l04p_0 vccaux io_l03n_0 io_l03p_0 io_l02n_0/vref_0 io_l02p_0 io_l01n_0 io_l01p_0 ip tck tdo 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 gnd 155 tms 154 ip 153 io_l16n_1/ldc2 152 io_l16p_1/ldc1 151 io_l15n_1/ldc0 150 io_l15p_1/hdc 149 vccaux 148 ip 147 io_l14n_1 146 io_l14p_1 145 io_l13n_1 144 io_l13p_1 143 vcco_1 142 ip 141 gnd 140 io_l12n_1/a0 139 io_l12p_1 138 io_l11n_1/a1 137 io_l11p_1/a2 136 ip/vref_1 o_l10n_1/a3/rhclk7 o_l10p_1/a4/rhclk6 o_l09n_1/a5/rhclk5 o_l09p_1/a6/rhclk4 131 gnd 130 ip o_l08n_1/a7/rhclk3 o_l08p_1/a8/rhclk2 o_l07n_1/a9/rhclk1 o_l07p_1/a10/rhclk 125 vcco_1 124 ip 123 io_l06n_1/vref_1 122 io_l06p_1 121 gnd 120 io_l05n_1/a11 119 io_l05p_1/a12 118 ip 117 vccint 116 io_l04n_1 115 io_l04p_1 114 vcco_1 113 io_l03n_1/vref_1 112 io_l03p_1 111 vccaux 110 ip 109 io_l02n_1/a13 108 io_l02p_1/a14 107 io_l01n_1/a15 106 io_l01p_1/a16 105 gnd 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 ip_l10p_2/rdwr_b/gclk0 ip_l10n_2/m2/gclk1 io_l11p_2/d2/gclk2 io_l11n_2/d1/gclk3 io/m1 gnd io_l12p_2/m0 io_l12n_2/din/d0 vcco_2 io_l13p_2 io_l13n_2 ip vccaux io_l14p_2/a23 io_l14n_2/a22 gnd io_l15p_2/a21 io_l15n_2/a20 io/vref_2 io_l16p_2/vs2/a19 io_l16n_2/vs1/a18 ip io_l17p_2/vs0/a17 io_l17n_2/cclk done bank 1 bank 0 bank 2 80 81 82 83 126 i 127 i 128 i 129 i 132 i 133 i 134 i 135 i ds312-4_04_030705 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 27 advance product specification r ft256: 256-ball fine-pitch, thin ball grid array the 256-lead fine-pitch, thin ball grid array package, ft256, supports three different spartan-3e fpgas, including the xc3s250e, the xc3s500e, and the xc3s1200e. ta b l e 1 9 lists all the package pins. they are sorted by bank number and then by pin name of the largest device. pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. the highlighted rows indicate pinout differences between the xc3s250e, the xc3s500e, and the xc3s1200e fpgas. the xc3s250e has 18 unconnected balls, indi- cated as n.c. (no connection) in ta b l e 1 9 and with the black diamond character ( ) in both ta b l e 1 9 and in figure 7 . if the table row is highlighted in tan, then this is an instance where an unconnected pin on the xc3s250e fpga maps to a vref pin on the xc3s500e and xc3s1200e fpga. if the fpga application uses an i/o standard that requires a vref voltage reference, connect the highlighted pin to the vref voltage supply, even though this does not actually connect to the xc3s250e fpga. this vref connection on the board allows future migration to the larger devices with- out modifying the printed-circuit board. all other balls have nearly identical functionality on all three devices. ta b l e 2 3 summarizes the spartan-3e footprint migration differences for the ft256 package. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip . pinout table table 19: ft256 package pinout bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type 0 io io io a7 i/o 0 io io io a12 i/o 0 io io io b4 i/o 0 ip ip io b6 250e: input 500e: input 1200e: i/o 0 ip ip io b10 250e: input 500e: input 1200e: i/o 0 io/vref_0 io/vref_0 io/vref_0 d9 vref 0 io_l01n_0 io_l01n_0 io_l01n_0 a14 i/o 0 io_l01p_0 io_l01p_0 io_l01p_0 b14 i/o 0 io_l03n_0/vref_0 io_l03n_0/vref_0 io_l03n_0/vref_0 a13 vref 0 io_l03p_0 io_l03p_0 io_l03p_0 b13 i/o 0 io_l04n_0 io_l04n_0 io_l04n_0 e11 i/o 0 io_l04p_0 io_l04p_0 io_l04p_0 d11 i/o 0 io_l05n_0/vref_0 io_l05n_0/vref_0 io_l05n_0/vref_0 b11 vref 0 io_l05p_0 io_l05p_0 io_l05p_0 c11 i/o 0 io_l06n_0 io_l06n_0 io_l06n_0 e10 i/o 0 io_l06p_0 io_l06p_0 io_l06p_0 d10 i/o 0 io_l08n_0/gclk5 io_l08n_0/gclk5 io_l08n_0/gclk5 f9 gclk 0 io_l08p_0/gclk4 io_l08p_0/gclk4 io_l08p_0/gclk4 e9 gclk 0 io_l09n_0/gclk7 io_l09n_0/gclk7 io_l09n_0/gclk7 a9 gclk pinout descriptions 28 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 0 io_l09p_0/gclk6 io_l09p_0/gclk6 io_l09p_0/gclk6 a10 gclk 0 io_l11n_0/gclk11 io_l11n_0/gclk11 io_l11n_0/gclk11 d8 gclk 0 io_l11p_0/gclk10 io_l11p_0/gclk10 io_l11p_0/gclk10 c8 gclk 0 io_l12n_0 io_l12n_0 io_l12n_0 f8 i/o 0 io_l12p_0 io_l12p_0 io_l12p_0 e8 i/o 0 n.c. ( ) io_l13n_0 io_l13n_0 c7 250e: n.c. 500e: i/o 1200e: i/o 0 n.c. ( ) io_l13p_0 io_l13p_0 b7 250e: n.c. 500e: i/o 1200e: i/o 0 io_l14n_0/vref_0 io_l14n_0/vref_0 io_l14n_0/vref_0 d7 vref 0 io_l14p_0 io_l14p_0 io_l14p_0 e7 i/o 0 io_l15n_0 io_l15n_0 io_l15n_0 d6 i/o 0 io_l15p_0 io_l15p_0 io_l15p_0 c6 i/o 0 io_l17n_0/vref_0 io_l17n_0/vref_0 io_l17n_0/vref_0 a4 vref 0 io_l17p_0 io_l17p_0 io_l17p_0 a5 i/o 0 io_l18n_0 io_l18n_0 io_l18n_0 c4 i/o 0 io_l18p_0 io_l18p_0 io_l18p_0 c5 i/o 0 io_l19n_0/hswap io_l19n_0/hswap io_l19n_0/hswap b3 dual 0 io_l19p_0 io_l19p_0 io_l19p_0 c3 i/o 0 ip ip ip a3 input 0 ip ip ip c13 input 0 ip_l02n_0 ip_l02n_0 ip_l02n_0 c12 input 0 ip_l02p_0 ip_l02p_0 ip_l02p_0 d12 input 0 ip_l07n_0 ip_l07n_0 ip_l07n_0 c9 input 0 ip_l07p_0 ip_l07p_0 ip_l07p_0 c10 input 0 ip_l10n_0/gclk9 ip_l10n_0/gclk9 ip_l10n_0/gclk9 b8 gclk 0 ip_l10p_0/gclk8 ip_l10p_0/gclk8 ip_l10p_0/gclk8 a8 gclk 0 ip_l16n_0 ip_l16n_0 ip_l16n_0 e6 input 0 ip_l16p_0 ip_l16p_0 ip_l16p_0 d5 input 0 vcco_0 vcco_0 vcco_0 b5 vcco 0 vcco_0 vcco_0 vcco_0 b12 vcco 0 vcco_0 vcco_0 vcco_0 f7 vcco 0 vcco_0 vcco_0 vcco_0 f10 vcco 1 io_l01n_1/a15 io_l01n_1/a15 io_l01n_1/a15 r15 dual table 19: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 29 advance product specification r 1 io_l01p_1/a16 io_l01p_1/a16 io_l01p_1/a16 r16 dual 1 io_l02n_1/a13 io_l02n_1/a13 io_l02n_1/a13 p15 dual 1 io_l02p_1/a14 io_l02p_1/a14 io_l02p_1/a14 p16 dual 1 n.c. ( ) io_l03n_1/vref_1 io_l03n_1/vref_1 n15 250e: n.c. 500e: vref 1200e: vref 1 n.c. ( ) io_l03p_1 io_l03p_1 n14 250e: n.c. 500e: i/o 1200e: i/o 1 io_l04n_1/vref_1 io_l04n_1/vref_1 io_l04n_1/vref_1 m16 vref 1 io_l04p_1 io_l04p_1 io_l04p_1 n16 i/o 1 n.c. ( ) io_l05n_1 io_l05n_1 l13 250e: n.c. 500e: i/o 1200e: i/o 1 n.c. ( ) io_l05p_1 io_l05p_1 l12 250e: n.c. 500e: i/o 1200e: i/o 1 io_l06n_1 io_l06n_1 io_l06n_1 l15 i/o 1 io_l06p_1 io_l06p_1 io_l06p_1 l14 i/o 1 io_l07n_1/a11 io_l07n_1/a11 io_l07n_1/a11 k12 dual 1 io_l07p_1/a12 io_l07p_1/a12 io_l07p_1/a12 k13 dual 1 io_l08n_1/vref_1 io_l08n_1/vref_1 io_l08n_1/vref_1 k14 vref 1 io_l08p_1 io_l08p_1 io_l08p_1 k15 i/o 1 io_l09n_1/a9/rhclk1 io_l09n_1/a9/rhclk1 io_l09n_1/a9/rhclk1 j16 rhclk/dual 1 io_l09p_1/a10/rhclk0 io_l09p_1/a10/rhclk0 io_l09p_1/a10/rhclk0 k16 rhclk/dual 1 io_l10n_1/a7/rhclk3/ trdy1 io_l10n_1/a7/rhclk3/ trdy1 io_l10n_1/a7/rhclk3/ trdy1 j13 rhclk/dual 1 io_l10p_1/a8/rhclk2 io_l10p_1/a8/rhclk2 io_l10p_1/a8/rhclk2 j14 rhclk/dual 1 io_l11n_1/a5/rhclk5 io_l11n_1/a5/rhclk5 io_l11n_1/a5/rhclk5 h14 rhclk/dual 1 io_l11p_1/a6/rhclk4/ irdy1 io_l11p_1/a6/rhclk4/ irdy1 io_l11p_1/a6/rhclk4/ irdy1 h15 rhclk/dual 1 io_l12n_1/a3/rhclk7 io_l12n_1/a3/rhclk7 io_l12n_1/a3/rhclk7 h11 rhclk/dual 1 io_l12p_1/a4/rhclk6 io_l12p_1/a4/rhclk6 io_l12p_1/a4/rhclk6 h12 rhclk/dual 1 io_l13n_1/a1 io_l13n_1/a1 io_l13n_1/a1 g16 dual 1 io_l13p_1/a2 io_l13p_1/a2 io_l13p_1/a2 g15 dual 1 io_l14n_1/a0 io_l14n_1/a0 io_l14n_1/a0 g14 dual 1 io_l14p_1 io_l14p_1 io_l14p_1 g13 i/o 1 io_l15n_1 io_l15n_1 io_l15n_1 f15 i/o table 19: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions 30 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 1 io_l15p_1 io_l15p_1 io_l15p_1 f14 i/o 1 io_l16n_1 io_l16n_1 io_l16n_1 f12 i/o 1 io_l16p_1 io_l16p_1 io_l16p_1 f13 i/o 1 n.c. ( ) io_l17n_1 io_l17n_1 e16 250e: n.c. 500e: i/o 1200e: i/o 1 n.c. ( ). io_l17p_1 io_l17p_1 e13 250e: n.c. 500e: i/o 1200e: i/o 1 io_l18n_1/ldc0 io_l18n_1/ldc0 io_l18n_1/ldc0 d14 dual 1 io_l18p_1/hdc io_l18p_1/hdc io_l18p_1/hdc d15 dual 1 io_l19n_1/ldc2 io_l19n_1/ldc2 io_l19n_1/ldc2 c15 dual 1 io_l19p_1/ldc1 io_l19p_1/ldc1 io_l19p_1/ldc1 c16 dual 1 ip ip ip b16 input 1 ip ip ip e14 input 1 ip ip ip g12 input 1 ip ip ip h16 input 1 ip ip ip j11 input 1 ip ip ip j12 input 1 ip ip ip m13 input 1 io io ip m14 250e: i/o 500e: i/o 1200e: input 1 io/vref_1 ip/vref_1 ip/vref_1 d16 250e: vref(i/o) 500e: vref(input) 1200e: vref(input) 1 ip/vref_1 ip/vref_1 ip/vref_1 h13 vref 1 vcco_1 vcco_1 vcco_1 e15 vcco 1 vcco_1 vcco_1 vcco_1 g11 vcco 1 vcco_1 vcco_1 vcco_1 k11 vcco 1 vcco_1 vcco_1 vcco_1 m15 vcco 2 ip ip io m7 250e: input 500e: input 1200e: i/o 2 ip ip io t12 250e: input 500e: input 1200e: i/o table 19: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 31 advance product specification r 2 io/d5 io/d5 io/d5 t8 dual 2 io/m1 io/m1 io/m1 t10 dual 2 io/vref_2 io/vref_2 io/vref_2 p13 vref 2 io/vref_2 io/vref_2 io/vref_2 r4 vref 2 io_l01n_2/init_b io_l01n_2/init_b io_l01n_2/init_b p4 dual 2 io_l01p_2/cso_b io_l01p_2/cso_b io_l01p_2/cso_b p3 dual 2 io_l03n_2/mosi/csi_b io_l03n_2/mosi/csi_b io_l03n_2/mosi/csi_b n5 dual 2 io_l03p_2/dout/busy io_l03p_2/dout/busy io_l03p_2/dout/busy p5 dual 2 io_l04n_2 io_l04n_2 io_l04n_2 t5 i/o 2 io_l04p_2 io_l04p_2 io_l04p_2 t4 i/o 2 io_l05n_2 io_l05n_2 io_l05n_2 n6 i/o 2 io_l05p_2 io_l05p_2 io_l05p_2 m6 i/o 2 io_l06n_2 io_l06n_2 io_l06n_2 p6 i/o 2 io_l06p_2 io_l06p_2 io_l06p_2 r6 i/o 2 n.c. ( ) io_l07n_2 io_l07n_2 p7 250e: n.c. 500e: i/o 1200e: i/o 2 n.c. ( ) io_l07p_2 io_l07p_2 n7 250e: n.c. 500e: i/o 1200e: i/o 2 io_l09n_2/d6/gclk13 io_l09n_2/d6/gclk13 io_l09n_2/d6/gclk13 l8 dual/gclk 2 io_l09p_2/d7/gclk12 io_l09p_2/d7/gclk12 io_l09p_2/d7/gclk12 m8 dual/gclk 2 io_l10n_2/d3/gclk15 io_l10n_2/d3/gclk15 io_l10n_2/d3/gclk15 p8 dual/gclk 2 io_l10p_2/d4/gclk14 io_l10p_2/d4/gclk14 io_l10p_2/d4/gclk14 n8 dual/gclk 2 io_l12n_2/d1/gclk3 io_l12n_2/d1/gclk3 io_l12n_2/d1/gclk3 n9 dual/gclk 2 io_l12p_2/d2/gclk2 io_l12p_2/d2/gclk2 io_l12p_2/d2/gclk2 p9 dual/gclk 2 io_l13n_2/din/d0 io_l13n_2/din/d0 io_l13n_2/din/d0 m9 dual 2 io_l13p_2/m0 io_l13p_2/m0 io_l13p_2/m0 l9 dual 2 n.c. ( ) io_l14n_2/vref_2 io_l14n_2/vref_2 r10 250e: n.c. 500e: vref 1200e: vref 2 n.c. ( ) io_l14p_2 io_l14p_2 p10 250e: n.c. 500e: i/o 1200e: i/o 2 io_l15n_2 io_l15n_2 io_l15n_2 m10 i/o 2 io_l15p_2 io_l15p_2 io_l15p_2 n10 i/o 2 io_l16n_2/a22 io_l16n_2/a22 io_l16n_2/a22 p11 dual table 19: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions 32 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 2 io_l16p_2/a23 io_l16p_2/a23 io_l16p_2/a23 r11 dual 2 io_l18n_2/a20 io_l18n_2/a20 io_l18n_2/a20 n12 dual 2 io_l18p_2/a21 io_l18p_2/a21 io_l18p_2/a21 p12 dual 2 io_l19n_2/vs1/a18 io_l19n_2/vs1/a18 io_l19n_2/vs1/a18 r13 dual 2 io_l19p_2/vs2/a19 io_l19p_2/vs2/a19 io_l19p_2/vs2/a19 t13 dual 2 io_l20n_2/cclk io_l20n_2/cclk io_l20n_2/cclk r14 dual 2 io_l20p_2/vs0/a17 io_l20p_2/vs0/a17 io_l20p_2/vs0/a17 p14 dual 2 ip ip ip t2 input 2 ip ip ip t14 input 2 ip_l02n_2 ip_l02n_2 ip_l02n_2 r3 input 2 ip_l02p_2 ip_l02p_2 ip_l02p_2 t3 input 2 ip_l08n_2/vref_2 ip_l08n_2/vref_2 ip_l08n_2/vref_2 t7 vref 2 ip_l08p_2 ip_l08p_2 ip_l08p_2 r7 input 2 ip_l11n_2/m2/gclk1 ip_l11n_2/m2/gclk1 ip_l11n_2/m2/gclk1 r9 dual/gclk 2 ip_l11p_2/rdwr_b/ gclk0 ip_l11p_2/rdwr_b/ gclk0 ip_l11p_2/rdwr_b/ gclk0 t9 dual/gclk 2 ip_l17n_2 ip_l17n_2 ip_l17n_2 m11 input 2 ip_l17p_2 ip_l17p_2 ip_l17p_2 n11 input 2 vcco_2 vcco_2 vcco_2 l7 vcco 2 vcco_2 vcco_2 vcco_2 l10 vcco 2 vcco_2 vcco_2 vcco_2 r5 vcco 2 vcco_2 vcco_2 vcco_2 r12 vcco 3 io_l01n_3 io_l01n_3 io_l01n_3 b2 i/o 3 io_l01p_3 io_l01p_3 io_l01p_3 b1 i/o 3 io_l02n_3/vref_3 io_l02n_3/vref_3 io_l02n_3/vref_3 c2 vref 3 io_l02p_3 io_l02p_3 io_l02p_3 c1 i/o 3 io_l03n_3 io_l03n_3 io_l03n_3 e4 i/o 3 io_l03p_3 io_l03p_3 io_l03p_3 e3 i/o 3 n.c. ( ) io_l04n_3/vref_3 io_l04n_3/vref_3 f4 250e: n.c. 500e: vref 1200e: vref 3 n.c. ( ) io_l04p_3 io_l04p_3 f3 250e: n.c. 500e: i/o 1200e: i/o 3 io_l05n_3 io_l05n_3 io_l05n_3 e1 i/o 3 io_l05p_3 io_l05p_3 io_l05p_3 d1 i/o table 19: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 33 advance product specification r 3 io_l06n_3 io_l06n_3 io_l06n_3 g4 i/o 3 io_l06p_3 io_l06p_3 io_l06p_3 g5 i/o 3 io_l07n_3 io_l07n_3 io_l07n_3 g2 i/o 3 io_l07p_3 io_l07p_3 io_l07p_3 g3 i/o 3 io_l08n_3/lhclk1 io_l08n_3/lhclk1 io_l08n_3/lhclk1 h6 lhclk 3 io_l08p_3/lhclk0 io_l08p_3/lhclk0 io_l08p_3/lhclk0 h5 lhclk 3 io_l09n_3/lhclk3/ irdy2 io_l09n_3/lhclk3/ irdy2 io_l09n_3/lhclk3/ irdy2 h4 lhclk 3 io_l09p_3/lhclk2 io_l09p_3/lhclk2 io_l09p_3/lhclk2 h3 lhclk 3 io_l10n_3/lhclk5 io_l10n_3/lhclk5 io_l10n_3/lhclk5 j3 lhclk 3 io_l10p_3/lhclk4/ trdy2 io_l10p_3/lhclk4/ trdy2 io_l10p_3/lhclk4/ trdy2 j2 lhclk 3 io_l11n_3/lhclk7 io_l11n_3/lhclk7 io_l11n_3/lhclk7 j4 lhclk 3 io_l11p_3/lhclk6 io_l11p_3/lhclk6 io_l11p_3/lhclk6 j5 lhclk 3 io_l12n_3 io_l12n_3 io_l12n_3 k1 i/o 3 io_l12p_3 io_l12p_3 io_l12p_3 j1 i/o 3 io_l13n_3 io_l13n_3 io_l13n_3 k3 i/o 3 io_l13p_3 io_l13p_3 io_l13p_3 k2 i/o 3 n.c. ( ) io_l14n_3/vref_3 io_l14n_3/vref_3 l2 250e: n.c. 500e: vref 1200e: vref 3 n.c. ( ) io_l14p_3 io_l14p_3 l3 250e: n.c. 500e: i/o 1200e: i/o 3 io_l15n_3 io_l15n_3 io_l15n_3 l5 i/o 3 io_l15p_3 io_l15p_3 io_l15p_3 k5 i/o 3 io_l16n_3 io_l16n_3 io_l16n_3 n1 i/o 3 io_l16p_3 io_l16p_3 io_l16p_3 m1 i/o 3 n.c. ( ) io_l17n_3 io_l17n_3 l4 250e: n.c. 500e: i/o 1200e: i/o 3 n.c. ( ) io_l17p_3 io_l17p_3 m4 250e: n.c. 500e: i/o 1200e: i/o 3 io_l18n_3 io_l18n_3 io_l18n_3 p1 i/o 3 io_l18p_3 io_l18p_3 io_l18p_3 p2 i/o 3 io_l19n_3 io_l19n_3 io_l19n_3 r1 i/o 3 io_l19p_3 io_l19p_3 io_l19p_3 r2 i/o table 19: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions 34 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 3 ip ip ip d2 input 3 ip ip ip f2 input 3 io io ip f5 250e: i/o 500e: i/o 1200e: input 3 ip ip ip h1 input 3 ip ip ip j6 input 3 ip ip ip k4 input 3 ip ip ip m3 input 3 ip ip ip n3 input 3 ip/vref_3 ip/vref_3 ip/vref_3 g1 vref 3 io/vref_3 io/vref_3 ip/vref_3 n2 250e: vref(i/o) 500e: vref(i/o) 1200e: vref(input) 3 vcco_3 vcco_3 vcco_3 e2 vcco 3 vcco_3 vcco_3 vcco_3 g6 vcco 3 vcco_3 vcco_3 vcco_3 k6 vcco 3 vcco_3 vcco_3 vcco_3 m2 vcco gnd gnd gnd gnd a1 gnd gnd gnd gnd gnd a16 gnd gnd gnd gnd gnd b9 gnd gnd gnd gnd gnd f6 gnd gnd gnd gnd gnd f11 gnd gnd gnd gnd gnd g7 gnd gnd gnd gnd gnd g8 gnd gnd gnd gnd gnd g9 gnd gnd gnd gnd gnd g10 gnd gnd gnd gnd gnd h2 gnd gnd gnd gnd gnd h7 gnd gnd gnd gnd gnd h8 gnd gnd gnd gnd gnd h9 gnd gnd gnd gnd gnd h10 gnd gnd gnd gnd gnd j7 gnd gnd gnd gnd gnd j8 gnd gnd gnd gnd gnd j9 gnd table 19: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 35 advance product specification r gnd gnd gnd gnd j10 gnd gnd gnd gnd gnd j15 gnd gnd gnd gnd gnd k7 gnd gnd gnd gnd gnd k8 gnd gnd gnd gnd gnd k9 gnd gnd gnd gnd gnd k10 gnd gnd gnd gnd gnd l6 gnd gnd gnd gnd gnd l11 gnd gnd gnd gnd gnd r8 gnd gnd gnd gnd gnd t1 gnd gnd gnd gnd gnd t16 gnd vccaux done done done t15 config vccaux prog_b prog_b prog_b d3 config vccaux tck tck tck a15 jtag vccaux tdi tdi tdi a2 jtag vccaux tdo tdo tdo c14 jtag vccaux tms tms tms b15 jtag vccaux vccaux vccaux vccaux a6 vccaux vccaux vccaux vccaux vccaux a11 vccaux vccaux vccaux vccaux vccaux f1 vccaux vccaux vccaux vccaux vccaux f16 vccaux vccaux vccaux vccaux vccaux l1 vccaux vccaux vccaux vccaux vccaux l16 vccaux vccaux vccaux vccaux vccaux t6 vccaux vccaux vccaux vccaux vccaux t11 vccaux vccint vccint vccint vccint d4 vccint vccint vccint vccint vccint d13 vccint vccint vccint vccint vccint e5 vccint vccint vccint vccint vccint e12 vccint vccint vccint vccint vccint m5 vccint vccint vccint vccint vccint m12 vccint vccint vccint vccint vccint n4 vccint vccint vccint vccint vccint n13 vccint table 19: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions 36 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r user i/os by bank ta b l e 2 0 , ta bl e 2 1 , and ta b l e 2 2 indicate how the available user-i/o pins are distributed between the four i/o banks on the ft256 package. the xc3s250e fpga in the ft256 package has 18 uncon- nected balls, labeled with an ?n.c.? type. these pins are also indicated with the black diamond ( ) symbol in figure 7 . table 20: user i/os per bank on xc3s250e in the ft256 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 44 20 10 1 5 8 right 1 42 10 7 21 4 0 bottom 2 44 8 9 24 3 0 left 3 42 24 7 0 3 8 total 172 62 33 46 15 16 table 21: user i/os per bank on xc3s500e in the ft256 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 46 22 10 1 5 8 right 1 48 15 7 21 5 0 bottom 2 48 11 9 24 4 0 left 3 48 28 7 0 5 8 total 190 76 33 46 19 16 table 22: user i/os per bank on xc3s1200e in the ft256 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 46 24 8 1 5 8 right 1 48 14 8 21 5 0 bottom 2 48 13 7 24 4 0 left 3 48 27 8 0 5 8 total 190 78 31 46 19 16 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 37 advance product specification r footprint migration differences ta b l e 2 3 summarizes any footprint and functionality differ- ences between the xc3s250e, the xc3s500e, and the xc3s1200e fpgas that may affect easy migration between devices in the fg256 package. there are 26 such balls. all other pins not listed in ta b l e 2 3 unconditionally migrate between spartan-3e devices available in the ft256 package. the xc3s250e is duplicated on both the left and right sides of the table to show migrations to and from the xc3s500e and the xc3s1200e. the arrows indicate the direction for easy migration. a double-ended arrow ( ) indicates that the two pins have identical functionality. a left-facing arrow ( ) indicates that the pin on the device on the right uncon- ditionally migrates to the pin on the device on the left. it may be possible to migrate the opposite direction depending on the i/o configuration. for example, an i/o pin (type = i/o) can migrate to an input-only pin (type = input) if the i/o pin is configured as an input. table 23: ft256 footprint migration differences ft256 ball bank xc3s250e type migration xc3s500e type migration xc3s1200e type migration xc3s250e type b6 0 input input i/o input b7 0 n.c. i/o i/o n.c. b10 0 input input i/o input c7 0 n.c. i/o i/o n.c. d16 1 vref(i/o) vref(input) vref(input) vref(i/o) e13 1 n.c. i/o i/o n.c. e16 1 n.c. i/o i/o n.c. f3 3 n.c. i/o i/o n.c. f4 3 n.c. vref vref n.c. f5 3 i/o i/o input i/o l2 3 n.c. vref vref n.c. l3 3 n.c. i/o i/o n.c. l4 3 n.c. i/o i/o n.c. l12 1 n.c. i/o i/o n.c. l13 1 n.c. i/o i/o n.c. m4 3 n.c. i/o i/o n.c. m7 2 input input i/o input m14 1 i/o i/o input i/o n2 3 vref(i/o) vref(i/o) vref(input) vref(i/o) n7 2 n.c. i/o i/o n.c. n14 1 n.c. i/o i/o n.c. n15 1 n.c. vref vref n.c. p7 2 n.c. i/o i/o n.c. p10 2 n.c. i/o i/o n.c. r10 2 n.c. vref vref n.c. t12 2 input input i/o input differences 19 7 26 legend: this pin is identical on both the device on the left and the right. this pin can unconditionally migrate from the device on the left to the device on the right. migration in the other direction m ay be possible depending on how the pin is configured for the device on the right. this pin can unconditionally migrate from the device on the right to the device on the left. migration in the other direction m ay be possible depending on how the pin is configured for the device on the left. pinout descriptions 38 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r ft256 footprint figure 7: ft256 package footprint (top view) 12345678910111213141516 a gnd tdi input i/o l17n_0 vref_0 i/o l17p_0 vccaux i/o input l10p_0 gclk8 i/o l09n_0 gclk7 i/o l09p_0 gclk6 vccaux i/o i/o l03n_0 vref_0 i/o l01n_0 tck gnd b i/o l01p_3 i/o l01n_3 i/o l19n_0 hswap i/o vcco_0 input i/o l13p_0 input l10n_0 gclk9 gnd input i/o l05n_0 vref_0 vcco_0 i/o l03p_0 i/o l01p_0 tms input c i/o l02p_3 i/o l02n_3 vref_3 i/o l19p_0 i/o l18n_0 i/o l18p_0 i/o l15p_0 i/o l13n_0 i/o l11p_0 gclk10 input l07n_0 input l07p_0 i/o l05p_0 input l02n_0 input tdo i/o l19n_1 ldc2 i/o l19p_1 ldc1 d i/o l05p_3 input prog_b vccint input l16p_0 i/o l15n_0 i/o l14n_0 vref_0 i/o l11n_0 gclk11 i/o vref_0 i/o l06p_0 i/o l04p_0 input l02p_0 vccint i/o l18n_1 ldc0 i/o l18p_1 hdc input vref_1 e i/o l05n_3 vcco_3 i/o l03p_3 i/o l03n_3 vccint input l16n_0 i/o l14p_0 i/o l12p_0 i/o l08p_0 gclk4 i/o l06n_0 i/o l04n_0 vccint i/o l17p_1 input vcco_1 i/o l17n_1 f vccaux input i/o l04p_3 i/o l04n_3 vref_3 input gnd vcco_0 i/o l12n_0 i/o l08n_0 gclk5 vcco_0 gnd i/o l16n_1 i/o l16p_1 i/o l15p_1 i/o l15n_1 vccaux g input vref_3 i/o l07n_3 i/o l07p_3 i/o l06n_3 i/o l06p_3 vcco_3 gnd gnd gnd gnd vcco_1 input i/o l14p_1 i/o l14n_1 a0 i/o l13p_1 a2 i/o l13n_1 a1 h input gnd i/o l09p_3 lhclk2 i/o l09n_3 lhclk3 irdy2 i/o l08p_3 lhclk0 i/o l08n_3 lhclk1 gnd gnd gnd gnd input vref_1 input j i/o l12p_3 i/o l10p_3 lhclk4 trdy2 i/o l10n_3 lhclk5 i/o l11n_3 lhclk7 i/o l11p_3 lhclk6 input gnd gnd gnd gnd input input gnd k i/o l12n_3 i/o l13p_3 i/o l13n_3 input i/o l15p_3 vcco_3 gnd gnd gnd gnd vcco_1 i/o l07n_1 a11 i/o l07p_1 a12 i/o l08n_1 vref_1 i/o l08p_1 l vccaux i/o l14n_3 vref_3 i/o l14p_3 i/o l17n_3 i/o l15n_3 gnd vcco_2 i/o l13p_2 m0 vcco_2 gnd i/o l05p_1 i/o l05n_1 i/o l06p_1 i/o l06n_1 vccaux m i/o l16p_3 vcco_3 input i/o l17p_3 vccint i/o l05p_2 input i/o l13n_2 din d0 i/o l15n_2 input l17n_2 vccint input input vcco_1 i/o l04n_1 vref_1 n i/o l16n_3 input vref_3 input vccint i/o l03n_2 mosi csi_b i/o l05n_2 i/o l07p_2 i/o l15p_2 input l17p_2 i/o l18n_2 a20 vccint i/o l03p_1 i/o l03n_1 vref_1 i/o l04p_1 p i/o l18n_3 i/o l18p_3 i/o l01p_2 cso_b i/o l01n_2 init_b i/o l03p_2 dout busy i/o l06n_2 i/o l07n_2 i/o l14p_2 i/o l16n_2 a22 i/o l18p_2 a21 i/o vref_2 i/o l20p_2 vs0 a 17 i/o l02n_1 a13 i/o l02p_1 a14 r i/o l19n_3 i/o l19p_3 input l02n_2 i/o vref_2 vcco_2 i/o l06p_2 input l08p_2 gnd i/o l14n_2 vref_2 i/o l16p_2 a23 vcco_2 i/o l19n_2 vs1 a 18 i/o l20n_2 cclk i/o l01n_1 a15 i/o l01p_1 a16 t gnd input input l02p_2 i/o l04p_2 i/o l04n_2 vccaux input l08n_2 vref_2 i/o d5 i/o m1 vccaux input i/o l19p_2 vs2 a 19 input done gnd bank 3 bank 1 bank 0 bank 2 i/o l12n_1 3 rhclk7 a i/o l12p_1 rhclk6 a 4 i/o l10n_1 a rhclk3 7 trdy1 i/o l11n_1 a 5 rhclk5 i/o l10p_1 a 8 rhclk2 i/o l11p_1 6 rhclk4 irdy1 a i/o l09n_1 a 9 rhclk1 i/o l09p_1 a 10 rhclk0 i/o l09p_2 d7 gclk12 i/o l09n_2 gclk13 d6 i/o l10p_2 d4 gclk14 i/o l12n_2 d1 gclk3 i/o l10n_2 d3 gclk15 i/o l12p_2 d2 gclk2 gclk1 m2 input l11n_2 gclk0 rdwr_b l11p_2 input ds312-4_05_021705 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 8 vccint: internal core supply voltage (+1.2v) 28 gnd: ground 16 vcco: output voltage supply for bank 8 vccaux: auxiliary supply voltage (+2.5v) 6 migration difference: for flexible package migration, use these pins as inputs. 18 unconnected pins on xc3s250e pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 39 advance product specification r fg320: 320-ball fine-pitch ball grid array the 320-lead fine-pitch ball grid array package, fg320, supports three different spartan-3e fpgas, including the xc3s500e, the xc3s1200e, and the xc3s1600e, as shown in ta bl e 2 4 and figure 8 . the fg320 package is an 18 x 18 array of solder balls minus the four center balls. ta b l e 2 4 lists all the package pins. they are sorted by bank number and then by pin name of the largest device. pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. the highlighted rows indicate pinout differences between the xc3s500e, the xc3s1200e, and the xc3s1600e fpgas. the xc3s500e has 18 unconnected balls, indi- cated as n.c. (no connection) in ta b l e 2 4 and with the black diamond character ( ) in both ta b l e 2 4 and in figure 8 . if the table row is highlighted in tan, then this is an instance where an unconnected pin on the xc3s500e fpga maps to a vref pin on the xc3s1200e and xc3s1600e fpga. if the fpga application uses an i/o standard that requires a vref voltage reference, connect the highlighted pin to the vref voltage supply, even though this does not actually connect to the xc3s500e fpga. this vref connection on the board allows future migration to the larger devices with- out modifying the printed-circuit board. all other balls have nearly identical functionality on all three devices. ta b l e 2 3 summarizes the spartan-3e footprint migration differences for the fg32 0 package. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip . pinout table table 24: fg320 package pinout bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type 0 ip io io a7 500e: input 1200e: i/o 1600e: i/o 0 io io io a8 i/o 0 io io io a11 i/o 0 io io io c4 i/o 0 ip io io d13 500e: input 1200e: i/o 1600e: i/o 0 io io io e13 i/o 0 io io io g9 i/o 0 io/vref_0 io/vref_0 io/vref_0 b11 vref 0 io_l01n_0 io_l01n_0 io_l01n_0 a16 i/o 0 io_l01p_0 io_l01p_0 io_l01p_0 b16 i/o 0 io_l03n_0/vref_0 io_l03n_0/vref_0 io_l03n_0/vref_0 c14 vref 0 io_l03p_0 io_l03p_0 io_l03p_0 d14 i/o 0 io_l04n_0 io_l04n_0 io_l04n_0 a14 i/o 0 io_l04p_0 io_l04p_0 io_l04p_0 b14 i/o 0 io_l05n_0/vref_0 io_l05n_0/vref_0 io_l05n_0/vref_0 b13 vref 0 io_l05p_0 io_l05p_0 io_l05p_0 a13 i/o 0 io_l06n_0 io_l06n_0 io_l06n_0 e12 i/o 0 io_l06p_0 io_l06p_0 io_l06p_0 f12 i/o pinout descriptions 40 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 0 io_l08n_0 io_l08n_0 io_l08n_0 f11 i/o 0 io_l08p_0 io_l08p_0 io_l08p_0 e11 i/o 0 io_l09n_0 io_l09n_0 io_l09n_0 d11 i/o 0 io_l09p_0 io_l09p_0 io_l09p_0 c11 i/o 0 io_l11n_0/gclk5 io_l11n_0/gclk5 io_l11n_0/gclk5 e10 gclk 0 io_l11p_0/gclk4 io_l11p_0/gclk4 io_l11p_0/gclk4 d10 gclk 0 io_l12n_0/gclk7 io_l12n_0/gclk7 io_l12n_0/gclk7 a10 gclk 0 io_l12p_0/gclk6 io_l12p_0/gclk6 io_l12p_0/gclk6 b10 gclk 0 io_l14n_0/gclk11 io_l14n_0/gclk11 io_l14n_0/gclk11 d9 gclk 0 io_l14p_0/gclk10 io_l14p_0/gclk10 io_l14p_0/gclk10 c9 gclk 0 io_l15n_0 io_l15n_0 io_l15n_0 f9 i/o 0 io_l15p_0 io_l15p_0 io_l15p_0 e9 i/o 0 io_l17n_0 io_l17n_0 io_l17n_0 f8 i/o 0 io_l17p_0 io_l17p_0 io_l17p_0 e8 i/o 0 io_l18n_0/vref_0 io_l18n_0/vref_0 io_l18n_0/vref_0 d7 vref 0 io_l18p_0 io_l18p_0 io_l18p_0 c7 i/o 0 io_l19n_0/vref_0 io_l19n_0/vref_0 io_l19n_0/vref_0 e7 vref 0 io_l19p_0 io_l19p_0 io_l19p_0 f7 i/o 0 io_l20n_0 io_l20n_0 io_l20n_0 a6 i/o 0 io_l20p_0 io_l20p_0 io_l20p_0 b6 i/o 0 n.c. ( ? ) io_l21n_0 io_l21n_0 e6 500e: n.c. 1200e: i/o 1600e: i/o 0 n.c. ( ? ) io_l21p_0 io_l21p_0 d6 500e: n.c. 1200e: i/o 1600e: i/o 0 io_l23n_0/vref_0 io_l23n_0/vref_0 io_l23n_0/vref_0 d5 vref 0 io_l23p_0 io_l23p_0 io_l23p_0 c5 i/o 0 io_l24n_0 io_l24n_0 io_l24n_0 b4 i/o 0 io_l24p_0 io_l24p_0 io_l24p_0 a4 i/o 0 io_l25n_0/hswap io_l25n_0/hswap io_l25n_0/hswap b3 dual 0 io_l25p_0 io_l25p_0 io_l25p_0 c3 i/o 0 ip ip ip a3 input 0 n.c. ( ? ) io ip a12 500e: n.c. 1200e: i/o 1600e: input table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 41 advance product specification r 0 ip ip ip c15 input 0 ip_l02n_0 ip_l02n_0 ip_l02n_0 a15 input 0 ip_l02p_0 ip_l02p_0 ip_l02p_0 b15 input 0 ip_l07n_0 ip_l07n_0 ip_l07n_0 d12 input 0 ip_l07p_0 ip_l07p_0 ip_l07p_0 c12 input 0 ip_l10n_0 ip_l10n_0 ip_l10n_0 g10 input 0 ip_l10p_0 ip_l10p_0 ip_l10p_0 f10 input 0 ip_l13n_0/gclk9 ip_l13n_0/gclk9 ip_l13n_0/gclk9 b9 gclk 0 ip_l13p_0/gclk8 ip_l13p_0/gclk8 ip_l13p_0/gclk8 b8 gclk 0 ip_l16n_0 ip_l16n_0 ip_l16n_0 d8 input 0 ip_l16p_0 ip_l16p_0 ip_l16p_0 c8 input 0 ip_l22n_0 ip_l22n_0 ip_l22n_0 b5 input 0 ip_l22p_0 ip_l22p_0 ip_l22p_0 a5 input 0 vcco_0 vcco_0 vcco_0 a9 vcco 0 vcco_0 vcco_0 vcco_0 c6 vcco 0 vcco_0 vcco_0 vcco_0 c13 vcco 0 vcco_0 vcco_0 vcco_0 g8 vcco 0 vcco_0 vcco_0 vcco_0 g11 vcco 1 n.c. ( ? ) io io p16 500e: n.c. 1200e: i/o 1600e: i/o 1 io_l01n_1/a15 io_l01n_1/a15 io_l01n_1/a15 t17 dual 1 io_l01p_1/a16 io_l01p_1/a16 io_l01p_1/a16 u18 dual 1 io_l02n_1/a13 io_l02n_1/a13 io_l02n_1/a13 t18 dual 1 io_l02p_1/a14 io_l02p_1/a14 io_l02p_1/a14 r18 dual 1 io_l03n_1/vref_1 io_l03n_1/vref_1 io_l03n_1/vref_1 r16 vref 1 io_l03p_1 io_l03p_1 io_l03p_1 r15 i/o 1 n.c. ( ? ) io_l04n_1 io_l04n_1 n14 500e: n.c. 1200e: i/o 1600e: input 1 n.c. ( ? ) io_l04p_1 io_l04p_1 n15 500e: n.c. 1200e: i/o 1600e: input 1 io_l05n_1/vref_1 io_l05n_1/vref_1 io_l05n_1/vref_1 m13 vref 1 io_l05p_1 io_l05p_1 io_l05p_1 m14 i/o 1 io_l06n_1 io_l06n_1 io_l06n_1 p18 i/o table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions 42 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 1 io_l06p_1 io_l06p_1 io_l06p_1 p17 i/o 1 io_l07n_1 io_l07n_1 io_l07n_1 m16 i/o 1 io_l07p_1 io_l07p_1 io_l07p_1 m15 i/o 1 io_l08n_1 io_l08n_1 io_l08n_1 m18 i/o 1 io_l08p_1 io_l08p_1 io_l08p_1 n18 i/o 1 io_l09n_1/a11 io_l09n_1/a11 io_l09n_1/a11 l15 dual 1 io_l09p_1/a12 io_l09p_1/a12 io_l09p_1/a12 l16 dual 1 io_l10n_1/vref_1 io_l10n_1/vref_1 io_l10n_1/vref_1 l17 vref 1 io_l10p_1 io_l10p_1 io_l10p_1 l18 i/o 1 io_l11n_1/a9/rhclk1 io_l11n_1/a9/rhclk1 io_l11n_1/a9/rhclk1 k12 rhclk/dual 1 io_l11p_1/a10/rhclk0 io_l11p_1/a10/rhclk0 io_l11p_1/a10/rhclk0 k13 rhclk/dual 1 io_l12n_1/a7/rhclk3/ trdy1 io_l12n_1/a7/rhclk3/ trdy1 io_l12n_1/a7/rhclk3/ trdy1 k14 rhclk/dual 1 io_l12p_1/a8/rhclk2 io_l12p_1/a8/rhclk2 io_l12p_1/a8/rhclk2 k15 rhclk/dual 1 io_l13n_1/a5/rhclk5 io_l13n_1/a5/rhclk5 io_l13n_1/a5/rhclk5 j16 rhclk/dual 1 io_l13p_1/a6/rhclk4/ irdy1 io_l13p_1/a6/rhclk4/ irdy1 io_l13p_1/a6/rhclk4/ irdy1 j17 rhclk/dual 1 io_l14n_1/a3/rhclk7 io_l14n_1/a3/rhclk7 io_l14n_1/a3/rhclk7 j14 rhclk/dual 1 io_l14p_1/a4/rhclk6 io_l14p_1/a4/rhclk6 io_l14p_1/a4/rhclk6 j15 rhclk/dual 1 io_l15n_1/a1 io_l15n_1/a1 io_l15n_1/a1 j13 dual 1 io_l15p_1/a2 io_l15p_1/a2 io_l15p_1/a2 j12 dual 1 io_l16n_1/a0 io_l16n_1/a0 io_l16n_1/a0 h17 dual 1 io_l16p_1 io_l16p_1 io_l16p_1 h16 i/o 1 io_l17n_1 io_l17n_1 io_l17n_1 h15 i/o 1 io_l17p_1 io_l17p_1 io_l17p_1 h14 i/o 1 io_l18n_1 io_l18n_1 io_l18n_1 g16 i/o 1 io_l18p_1 io_l18p_1 io_l18p_1 g15 i/o 1 io_l19n_1 io_l19n_1 io_l19n_1 f17 i/o 1 io_l19p_1 io_l19p_1 io_l19p_1 f18 i/o 1 io_l20n_1 io_l20n_1 io_l20n_1 g13 i/o 1 io_l20p_1 io_l20p_1 io_l20p_1 g14 i/o 1 io_l21n_1 io_l21n_1 io_l21n_1 f14 i/o 1 io_l21p_1 io_l21p_1 io_l21p_1 f15 i/o 1 n.c. ( ? ) io_l22n_1 io_l22n_1 e16 500e: n.c. 1200e: i/o 1600e: i/o table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 43 advance product specification r 1 n.c. ( ? ) io_l22p_1 io_l22p_1 e15 500e: n.c. 1200e: i/o 1600e: i/o 1 io_l23n_1/ldc0 io_l23n_1/ldc0 io_l23n_1/ldc0 d16 dual 1 io_l23p_1/hdc io_l23p_1/hdc io_l23p_1/hdc d17 dual 1 io_l24n_1/ldc2 io_l24n_1/ldc2 io_l24n_1/ldc2 c17 dual 1 io_l24p_1/ldc1 io_l24p_1/ldc1 io_l24p_1/ldc1 c18 dual 1 ip ip ip b18 input 1 io ip ip e17 500e: i/o 1200e: input 1600e: input 1 ip ip ip e18 input 1 ip ip ip g18 input 1 ip ip ip h13 input 1 ip ip ip k17 input 1 ip ip ip k18 input 1 ip ip ip l13 input 1 ip ip ip l14 input 1 ip ip ip n17 input 1 io ip ip p15 500e: i/o 1200e: input 1600e: input 1 ip ip ip r17 input 1 ip/vref_1 ip/vref_1 ip/vref_1 d18 vref 1 ip/vref_1 ip/vref_1 ip/vref_1 h18 vref 1 vcco_1 vcco_1 vcco_1 f16 vcco 1 vcco_1 vcco_1 vcco_1 h12 vcco 1 vcco_1 vcco_1 vcco_1 j18 vcco 1 vcco_1 vcco_1 vcco_1 l12 vcco 1 vcco_1 vcco_1 vcco_1 n16 vcco 2 io io io p9 i/o 2 io io io r11 i/o 2 ip io io u6 500e: input 1200e: i/o 1600e: i/o table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions 44 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 2 ip io io u13 500e: input 1200e: i/o 1600e: i/o 2 n.c. ( ? ) io io v7 500e: n.c. 1200e: i/o 1600e: i/o 2 io/d5 io/d5 io/d5 r9 dual 2 io/m1 io/m1 io/m1 v11 dual 2 io/vref_2 io/vref_2 io/vref_2 t15 vref 2 io/vref_2 io/vref_2 io/vref_2 u5 vref 2 io_l01n_2/init_b io_l01n_2/init_b io_l01n_2/init_b t3 dual 2 io_l01p_2/cso_b io_l01p_2/cso_b io_l01p_2/cso_b u3 dual 2 io_l03n_2/mosi/csi_b io_l03n_2/mosi/csi_b io_l03n_2/mosi/csi_b t4 dual 2 io_l03p_2/dout/busy io_l03p_2/dout/busy io_l03p_2/dout/busy u4 dual 2 io_l04n_2 io_l04n_2 io_l04n_2 t5 i/o 2 io_l04p_2 io_l04p_2 io_l04p_2 r5 i/o 2 io_l05n_2 io_l05n_2 io_l05n_2 p6 i/o 2 io_l05p_2 io_l05p_2 io_l05p_2 r6 i/o 2 n.c. ( ? ) io_l06n_2/vref_2 io_l06n_2/vref_2 v6 500e: n.c. 1200e: vref 1600e: vref 2 n.c. ( ? ) io_l06p_2 io_l06p_2 v5 500e: n.c. 1200e: i/o 1600e: i/o 2 io_l07n_2 io_l07n_2 io_l07n_2 p7 i/o 2 io_l07p_2 io_l07p_2 io_l07p_2 n7 i/o 2 io_l09n_2 io_l09n_2 io_l09n_2 n8 i/o 2 io_l09p_2 io_l09p_2 io_l09p_2 p8 i/o 2 io_l10n_2 io_l10n_2 io_l10n_2 t8 i/o 2 io_l10p_2 io_l10p_2 io_l10p_2 r8 i/o 2 io_l12n_2/d6/gclk13 io_l12n_2/d6/gclk13 io_l12n_2/d6/gclk13 m9 dual/gclk 2 io_l12p_2/d7/gclk12 io_l12p_2/d7/gclk12 io_l12p_2/d7/gclk12 n9 dual/gclk 2 io_l13n_2/d3/gclk15 io_l13n_2/d3/gclk15 io_l13n_2/d3/gclk15 v9 dual/gclk 2 io_l13p_2/d4/gclk14 io_l13p_2/d4/gclk14 io_l13p_2/d4/gclk14 u9 dual/gclk 2 io_l15n_2/d1/gclk3 io_l15n_2/d1/gclk3 io_l15n_2/d1/gclk3 p10 dual/gclk 2 io_l15p_2/d2/gclk2 io_l15p_2/d2/gclk2 io_l15p_2/d2/gclk2 r10 dual/gclk 2 io_l16n_2/din/d0 io_l16n_2/din/d0 io_l16n_2/din/d0 n10 dual table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 45 advance product specification r 2 io_l16p_2/m0 io_l16p_2/m0 io_l16p_2/m0 m10 dual 2 io_l18n_2 io_l18n_2 io_l18n_2 n11 i/o 2 io_l18p_2 io_l18p_2 io_l18p_2 p11 i/o 2 io_l19n_2/vref_2 io_l19n_2/vref_2 io_l19n_2/vref_2 v13 vref 2 io_l19p_2 io_l19p_2 io_l19p_2 v12 i/o 2 io_l20n_2 io_l20n_2 io_l20n_2 r12 i/o 2 io_l20p_2 io_l20p_2 io_l20p_2 t12 i/o 2 n.c. ( ? ) io_l21n_2 io_l21n_2 p12 500e: n.c. 1200e: i/o 1600e: i/o 2 n.c. ( ? ) io_l21p_2 io_l21p_2 n12 500e: n.c. 1200e: i/o 1600e: i/o 2 io_l22n_2/a22 io_l22n_2/a22 io_l22n_2/a22 r13 dual 2 io_l22p_2/a23 io_l22p_2/a23 io_l22p_2/a23 p13 dual 2 io_l24n_2/a20 io_l24n_2/a20 io_l24n_2/a20 r14 dual 2 io_l24p_2/a21 io_l24p_2/a21 io_l24p_2/a21 t14 dual 2 io_l25n_2/vs1/a18 io_l25n_2/vs1/a18 io_l25n_2/vs1/a18 u15 dual 2 io_l25p_2/vs2/a19 io_l25p_2/vs2/a19 io_l25p_2/vs2/a19 v15 dual 2 io_l26n_2/cclk io_l26n_2/cclk io_l26n_2/cclk u16 dual 2 io_l26p_2/vs0/a17 io_l26p_2/vs0/a17 io_l26p_2/vs0/a17 t16 dual 2 ip ip ip v2 input 2 ip ip ip v16 input 2 ip_l02n_2 ip_l02n_2 ip_l02n_2 v3 input 2 ip_l02p_2 ip_l02p_2 ip_l02p_2 v4 input 2 ip_l08n_2 ip_l08n_2 ip_l08n_2 r7 input 2 ip_l08p_2 ip_l08p_2 ip_l08p_2 t7 input 2 ip_l11n_2/vref_2 ip_l11n_2/vref_2 ip_l11n_2/vref_2 v8 vref 2 ip_l11p_2 ip_l11p_2 ip_l11p_2 u8 input 2 ip_l14n_2/m2/gclk1 ip_l14n_2/m2/gclk1 ip_l14n_2/m2/gclk1 t10 dual/gclk 2 ip_l14p_2/rdwr_b/ gclk0 ip_l14p_2/rdwr_b/ gclk0 ip_l14p_2/rdwr_b/ gclk0 u10 dual/gclk 2 ip_l17n_2 ip_l17n_2 ip_l17n_2 u11 input 2 ip_l17p_2 ip_l17p_2 ip_l17p_2 t11 input 2 ip_l23n_2 ip_l23n_2 ip_l23n_2 u14 input 2 ip_l23p_2 ip_l23p_2 ip_l23p_2 v14 input table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions 46 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 2 vcco_2 vcco_2 vcco_2 m8 vcco 2 vcco_2 vcco_2 vcco_2 m11 vcco 2 vcco_2 vcco_2 vcco_2 t6 vcco 2 vcco_2 vcco_2 vcco_2 t13 vcco 2 vcco_2 vcco_2 vcco_2 v10 vcco 3 n.c. ( ? ) io io d4 500e: n.c. 1200e: i/o 1600e: i/o 3 io_l01n_3 io_l01n_3 io_l01n_3 c2 i/o 3 io_l01p_3 io_l01p_3 io_l01p_3 c1 i/o 3 io_l02n_3/vref_3 io_l02n_3/vref_3 io_l02n_3/vref_3 d2 vref 3 io_l02p_3 io_l02p_3 io_l02p_3 d1 i/o 3 io_l03n_3 io_l03n_3 io_l03n_3 e1 i/o 3 io_l03p_3 io_l03p_3 io_l03p_3 e2 i/o 3 n.c. ( ? ) io_l04n_3 io_l04n_3 e3 500e: n.c. 1200e: i/o 1600e: i/o 3 n.c. ( ? ) io_l04p_3 io_l04p_3 e4 500e: n.c. 1200e: i/o 1600e: i/o 3 io_l05n_3 io_l05n_3 io_l05n_3 f2 i/o 3 io_l05p_3 io_l05p_3 io_l05p_3 f1 i/o 3 io_l06n_3/vref_3 io_l06n_3/vref_3 io_l06n_3/vref_3 g4 vref 3 io_l06p_3 io_l06p_3 io_l06p_3 g3 i/o 3 io_l07n_3 io_l07n_3 io_l07n_3 g5 i/o 3 io_l07p_3 io_l07p_3 io_l07p_3 g6 i/o 3 io_l08n_3 io_l08n_3 io_l08n_3 h5 i/o 3 io_l08p_3 io_l08p_3 io_l08p_3 h6 i/o 3 io_l09n_3 io_l09n_3 io_l09n_3 h3 i/o 3 io_l09p_3 io_l09p_3 io_l09p_3 h4 i/o 3 io_l10n_3 io_l10n_3 io_l10n_3 h1 i/o 3 io_l10p_3 io_l10p_3 io_l10p_3 h2 i/o 3 io_l11n_3/lhclk1 io_l11n_3/lhclk1 io_l11n_3/lhclk1 j4 lhclk 3 io_l11p_3/lhclk0 io_l11p_3/lhclk0 io_l11p_3/lhclk0 j5 lhclk 3 io_l12n_3/lhclk3/ irdy2 io_l12n_3/lhclk3/ irdy2 io_l12n_3/lhclk3/ irdy2 j2 lhclk 3 io_l12p_3/lhclk2 io_l12p_3/lhclk2 io_l12p_3/lhclk2 j1 lhclk table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 47 advance product specification r 3 io_l13n_3/lhclk5 io_l13n_3/lhclk5 io_l13n_3/lhclk5 k4 lhclk 3 io_l13p_3/lhclk4/ trdy2 io_l13p_3/lhclk4/ trdy2 io_l13p_3/lhclk4/ trdy2 k3 lhclk 3 io_l14n_3/lhclk7 io_l14n_3/lhclk7 io_l14n_3/lhclk7 k5 lhclk 3 io_l14p_3/lhclk6 io_l14p_3/lhclk6 io_l14p_3/lhclk6 k6 lhclk 3 io_l15n_3 io_l15n_3 io_l15n_3 l2 i/o 3 io_l15p_3 io_l15p_3 io_l15p_3 l1 i/o 3 io_l16n_3 io_l16n_3 io_l16n_3 l4 i/o 3 io_l16p_3 io_l16p_3 io_l16p_3 l3 i/o 3 io_l17n_3/vref_3 io_l17n_3/vref_3 io_l17n_3/vref_3 l5 vref 3 io_l17p_3 io_l17p_3 io_l17p_3 l6 i/o 3 io_l18n_3 io_l18n_3 io_l18n_3 m3 i/o 3 io_l18p_3 io_l18p_3 io_l18p_3 m4 i/o 3 io_l19n_3 io_l19n_3 io_l19n_3 m6 i/o 3 io_l19p_3 io_l19p_3 io_l19p_3 m5 i/o 3 io_l20n_3 io_l20n_3 io_l20n_3 n5 i/o 3 io_l20p_3 io_l20p_3 io_l20p_3 n4 i/o 3 io_l21n_3 io_l21n_3 io_l21n_3 p1 i/o 3 io_l21p_3 io_l21p_3 io_l21p_3 p2 i/o 3 n.c. ( ? ) io_l22n_3 io_l22n_3 p4 500e: n.c. 1200e: i/o 1600e: i/o 3 n.c. ( ? ) io_l22p_3 io_l22p_3 p3 500e: n.c. 1200e: i/o 1600e: i/o 3 io_l23n_3 io_l23n_3 io_l23n_3 r2 i/o 3 io_l23p_3 io_l23p_3 io_l23p_3 r3 i/o 3 io_l24n_3 io_l24n_3 io_l24n_3 t1 i/o 3 io_l24p_3 io_l24p_3 io_l24p_3 t2 i/o 3 ip ip ip d3 input 3 io ip ip f4 500e: i/o 1200e: input 1600e: input 3 ip ip ip f5 input 3 ip ip ip g1 input 3 ip ip ip j7 input 3 ip ip ip k2 input table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions 48 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 3 ip ip ip k7 input 3 ip ip ip m1 input 3 ip ip ip n1 input 3 ip ip ip n2 input 3 ip ip ip r1 input 3 ip ip ip u1 input 3 ip/vref_3 ip/vref_3 ip/vref_3 j6 vref 3 io/vref_3 ip/vref_3 ip/vref_3 r4 500e: vref(i/o) 1200e: vref(input) 1600e: vref(input) 3 vcco_3 vcco_3 vcco_3 f3 vcco 3 vcco_3 vcco_3 vcco_3 h7 vcco 3 vcco_3 vcco_3 vcco_3 k1 vcco 3 vcco_3 vcco_3 vcco_3 l7 vcco 3 vcco_3 vcco_3 vcco_3 n3 vcco gnd gnd gnd gnd a1 gnd gnd gnd gnd gnd a18 gnd gnd gnd gnd gnd b2 gnd gnd gnd gnd gnd b17 gnd gnd gnd gnd gnd c10 gnd gnd gnd gnd gnd g7 gnd gnd gnd gnd gnd g12 gnd gnd gnd gnd gnd h8 gnd gnd gnd gnd gnd h9 gnd gnd gnd gnd gnd h10 gnd gnd gnd gnd gnd h11 gnd gnd gnd gnd gnd j3 gnd gnd gnd gnd gnd j8 gnd gnd gnd gnd gnd j11 gnd gnd gnd gnd gnd k8 gnd gnd gnd gnd gnd k11 gnd gnd gnd gnd gnd k16 gnd gnd gnd gnd gnd l8 gnd gnd gnd gnd gnd l9 gnd table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 49 advance product specification r gnd gnd gnd gnd l10 gnd gnd gnd gnd gnd l11 gnd gnd gnd gnd gnd m7 gnd gnd gnd gnd gnd m12 gnd gnd gnd gnd gnd t9 gnd gnd gnd gnd gnd u2 gnd gnd gnd gnd gnd u17 gnd gnd gnd gnd gnd v1 gnd gnd gnd gnd gnd v18 gnd vccaux done done done v17 config vccaux prog_b prog_b prog_b b1 config vccaux tck tck tck a17 jtag vccaux tdi tdi tdi a2 jtag vccaux tdo tdo tdo c16 jtag vccaux tms tms tms d15 jtag vccaux vccaux vccaux vccaux b7 vccaux vccaux vccaux vccaux vccaux b12 vccaux vccaux vccaux vccaux vccaux g2 vccaux vccaux vccaux vccaux vccaux g17 vccaux vccaux vccaux vccaux vccaux m2 vccaux vccaux vccaux vccaux vccaux m17 vccaux vccaux vccaux vccaux vccaux u7 vccaux vccaux vccaux vccaux vccaux u12 vccaux vccint vccint vccint vccint e5 vccint vccint vccint vccint vccint e14 vccint vccint vccint vccint vccint f6 vccint vccint vccint vccint vccint f13 vccint vccint vccint vccint vccint n6 vccint vccint vccint vccint vccint n13 vccint vccint vccint vccint vccint p5 vccint vccint vccint vccint vccint p14 vccint table 24: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions 50 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r user i/os by bank ta b l e 2 5 , ta bl e 2 6 , and ta b l e 2 7 indicate how the available user-i/o pins are distributed between the four i/o banks on the fg320 package. footprint migration differences ta b l e 2 8 summarizes any footprint and functionality differ- ences between the xc3s500e, the xc3s1200e, and the xc3s1600e fpgas that may affect easy migration between devices available in the fg320 package. there are 26 such balls. all other pins not listed in ta b l e 2 8 uncondi- tionally migrate between spartan-3e devices available in the fg320 package. the xc3s500e is duplicated on both the left and right sides of the table to show migrations to and from the xc3s1200e and the xc3s1600e. the arrows indicate the direction for easy migration. a double-ended arrow ( ? ? ) indicates that the two pins have identical functionality. a left-facing arrow ( ? ) indicates that the pin on the device on the right uncon- ditionally migrates to the pin on the device on the left. it may be possible to migrate the opposite direction depending on the i/o configuration. for example, an i/o pin (type = i/o) table 25: user i/os per bank for xc3s500e in the fg320 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 58 29 14 1 6 8 right 1 58 22 10 21 5 0 bottom 2 58 17 13 24 4 0 left 3 58 34 11 0 5 8 total 232 102 48 46 20 16 table 26: user i/os per bank for xc3s1200e in the fg320 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 61 34 12 1 6 8 right 1 63 25 12 21 5 0 bottom 2 63 23 11 24 5 0 left 3 63 38 12 0 5 8 total 250 120 47 46 21 16 table 27: user i/os per bank for xc3s1600e in the fg320 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 61 33 13 1 6 8 right 1 63 25 12 21 5 0 bottom 2 63 23 11 24 5 0 left 3 63 38 12 0 5 8 total 250 119 48 46 21 16 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 51 advance product specification r can migrate to an input-only pin (type = input) if the i/o pin is configured as an input. table 28: fg320 footprint migration differences pin bank xc3s500e migration xc3s1200e migration xc3s1600e migration xc3s500e a7 0 input ? i/o ? ? i/o ? input a12 0 n.c. ? i/o ? input ? n.c. d4 3 n.c. ? i/o ? ? i/o ? n.c. d6 0 n.c. ? i/o ? ? i/o ? n.c. d13 0 input ? i/o ? ? i/o ? input e3 3 n.c. ? i/o ? ? i/o ? n.c. e4 3 n.c. ? i/o ? ? i/o ? n.c. e6 0 n.c. ? i/o ? ? i/o ? n.c. e15 1 n.c. ? i/o ? ? i/o ? n.c. e16 1 n.c. ? i/o ? ? i/o ? n.c. e17 1 i/o ? input ? ? input ? i/o f4 3 i/o ? input ? ? input ? i/o n12 2 n.c. ? i/o ? ? i/o ? n.c. n14 1 n.c. ? i/o ? ? i/o ? n.c. n15 1 n.c. ? i/o ? ? i/o ? n.c. p3 3 n.c. ? i/o ? ? i/o ? n.c. p4 3 n.c. ? i/o ? ? i/o ? n.c. p12 2 n.c. ? i/o ? ? i/o ? n.c. p15 1 i/o ? input ? ? input ? i/o p16 1 n.c. ? i/o ? ? i/o ? n.c. r4 3 vref(i/o) ? vref(input) ? ? vref(input) ? vref(i/o) u6 2 input ? i/o ? ? i/o ? input u13 2 input ? i/o ? ? i/o ? input v5 2 n.c. ? i/o ? ? i/o ? n.c. v6 2 n.c. ? vref ? ? vref ? n.c. v7 2 n.c. ? i/o ? ? i/o ? n.c. differences 26 1 26 legend: ? ? this pin is identical on both the device on the left and the right. ? this pin can unconditionally migrate from the device on the left to the device on the right. migration in the other direction m ay be possible depending on how the pin is configured for the device on the right. ? this pin can unconditionally migrate from the device on the right to the device on the left. migration in the other direction m ay be possible depending on how the pin is configured for the device on the left. pinout descriptions 52 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r fg320 footprint figure 8: fg320 package footprint (top view) 123456789101112131415161718 a gnd tdi input i/o l24p_0 input l22p_0 i/o l20n_0 input ? ? i/o vcco_0 i/o l12n_0 gclk7 i/o input ? ? ? i/o l05p_0 i/o l04n_0 input l02n_0 i/o l01n_0 tck gnd b prog_b gnd i/o l25n_0 hswap i/o l24n_0 input l22n_0 i/o l20p_0 vccaux input l13p_0 gclk8 input l13n_0 gclk9 i/o l12p_0 gclk6 i/o vref_0 vccaux i/o l05n_0 vref_0 i/o l04p_0 input l02p_0 i/o l01p_0 gnd input c i/o l01p_3 i/o l01n_3 i/o l25p_0 i/o i/o l23p_0 vcco_0 i/o l18p_0 input l16p_0 i/o l14p_0 gclk10 gnd i/o l09p_0 input l07p_0 vcco_0 i/o l03n_0 vref_0 input tdo i/o l24n_1 ldc2 i/o l24p_1 ldc1 d i/o l02p_3 i/o l02n_3 vref_3 input i/o ? i/o l23n_0 vref_0 i/o l21p_0 ? i/o l18n_0 vref_0 input l16n_0 i/o l14n_0 gclk11 i/o l11p_0 gclk4 i/o l09n_0 input l07n_0 input ? ? ? ? ? ? ? ? i/o l03p_0 tms i/o l23n_1 ldc0 i/o l23p_1 hdc input vref_1 e i/o l03n_3 i/o l03p_3 i/o l04n_3 ? i/o l04p_3 ? vccint i/o l21n_0 ? i/o l19n_0 vref_0 i/o l17p_0 i/o l15p_0 i/o l11n_0 gclk5 i/o l08p_0 i/o l06n_0 i/o vccint i/o l22p_1 ? i/o l22n_1 ? input ? ? ? ? ? ? ? ? input f i/o l05p_3 i/o l05n_3 vcco_3 input ? ? ? ? ? ? ? ? input vccint i/o l19p_0 i/o l17n_0 i/o l15n_0 input l10p_0 i/o l08n_0 i/o l06p_0 vccint i/o l21n_1 i/o l21p_1 vcco_1 i/o l19n_1 i/o l19p_1 g input vccaux i/o l06p_3 i/o l06n_3 vref_3 i/o l07n_3 i/o l07p_3 gnd vcco_0 i/o input l10n_0 vcco_0 gnd i/o l20n_1 i/o l20p_1 i/o l18p_1 i/o l18n_1 vccaux input h i/o l10n_3 i/o l10p_3 i/o l09n_3 i/o l09p_3 i/o l08n_3 i/o l08p_3 vcco_3 gnd gnd gnd gnd vcco_1 input i/o l17p_1 i/o l17n_1 i/o l16p_1 i/o l16n_1 a0 input vref_1 j i/o l12p_3 lhclk2 i/o l12n_3 lhclk3 irdy2 gnd i/o l11n_3 lhclk1 i/o l11p_3 lhclk0 input vref_3 input gnd gnd i/o l15p_1 a2 i/o l15n_1 a1 4 _1 vcco_1 k vcco_3 input i/o l13p_3 lhclk4 t rdy2 i/o l13n_3 lhclk5 i/o l14n_3 lhclk7 i/o l14p_3 lhclk6 input gnd gnd gnd input input l i/o l15p_3 i/o l15n_3 i/o l16p_3 i/o l16n_3 i/o l17n_3 vref_3 i/o l17p_3 vcco_3 gnd gnd gnd gnd vcco_1 input input i/o l09n_1 a11 i/o l09p_1 a12 i/o l10n_1 vref_1 i/o l10p_1 m input vccaux i/o l18n_3 i/o l18p_3 i/o l19p_3 i/o l19n_3 gnd vcco_2 i/o l16p_2 m0 vcco_2 gnd i/o l05n_1 vref_1 i/o l05p_1 i/o l07p_1 i/o l07n_1 vccaux i/o l08n_1 n input input vcco_3 i/o l20p_3 i/o l20n_3 vccint i/o l07p_2 i/o l09n_2 i/o i/o l16n_2 din d0 i/o l18n_2 i/o l21p_2 ? vccint i/o l04n_1 ? i/o l04p_1 ? vcco_1 input i/o l08p_1 p i/o l21n_3 i/o l21p_3 i/o l22p_3 ? i/o l22n_3 ? vccint i/o l05n_2 i/o l07n_2 i/o l09p_2 i/o i/o l18p_2 i/o l21n_2 ? i/o l22p_2 a23 vccint input ? ? ? ? ? ? ? ? i/o ? i/o l06p_1 i/o l06n_1 r input i/o l23n_3 i/o l23p_3 input vref_3 ? ? i/o l04p_2 i/o l05p_2 input l08n_2 i/o l10p_2 i/o d5 i/o i/o l20n_2 i/o l22n_2 a22 i/o l24n_2 a20 i/o l03p_1 i/o l03n_1 vref_1 input i/o l02p_1 a14 t i/o l24n_3 i/o l24p_3 i/o l01n_2 init_b i/o l03n_2 mosi csi_b i/o l04n_2 vcco_2 input l08p_2 i/o l10n_2 gnd input l17p_2 i/o l20p_2 vcco_2 i/o l24p_2 a21 i/o vref_2 i/o l26p_2 v s0 a 17 i/o l01n_1 a15 i/o l02n_1 a13 u input gnd i/o l01p_2 cso_b i/o l03p_2 dout busy i/o vref_2 input ? ? ? ? ? ? ? ? vccaux input l11p_2 input l17n_2 vccaux input ? ? ? ? ? ? ? ? input l23n_2 i/o l25n_2 vs1 a 18 i/o l26n_2 cclk gnd i/o l01p_1 a16 v gnd input input l02n_2 input l02p_2 i/o l06p_2 ? i/o l06n_2 vref_2 ? i/o ? input l11n_2 vref_2 vcco_2 i/o m1 i/o l19p_2 i/o l19n_2 vref_2 input l23p_2 i/o l25p_2 vs2 a19 input done gnd bank 0 bank 3 bank 1 bank 2 i/o l14n_1 a3 rhclk7 rhclk6 l14p_1 a 4 i/o l13n_1 a5 rhclk5 i/o i/o l13p a 6 rhclk4 irdy1 l11n_1 a9 rhclk1 i/o i/o l11p_1 rhclk0 a10 trdy1 rhclk3 a 7 l12n_1 i/o i/o l12p_1 rhclk2 a 8 i/o l12n_2 d6 gclk13 gclk12 d7 l12p_2 gclk3 d1 l15n_2 i/o gclk2 d2 l15p_2 i/o gclk1 m2 l14n_2 input gclk0 l14p_2 rdwr_b input gclk14 d4 l13p_2 i/o gclk15 d3 l13n_2 i/o ds312-4_06_021605 i/o: unrestricted, general-purpose user i/o 46 dual: configuration pin, then possible user-i/o vref: user i/o or input voltage reference for bank input: unrestricted, general-purpose input pin 16 gclk: user i/o, input, or global buffer input 20 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 8 vccint: internal core supply voltage (+1.2v) 0 n.c.: not connected 28 gnd: ground 8 vccaux: auxiliary supply voltage (+2.5v) pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 53 advance product specification r fg400: 400-ball fine-pitch ball grid array the 400-ball fine-pitch ball grid array, fg400, supports two different spartan-3e fpgas, including the xc3s1200e and the xc3s1600e. both devices share a common footprint for this package as shown in ta b l e 2 9 and figure 9 . ta b l e 2 9 lists all the fg400 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web- site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip . pinout table table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type 0io a3 i/o 0io a8 i/o 0io a12 i/o 0io c7 i/o 0io c10 i/o 0io e8 i/o 0io e13 i/o 0io e16 i/o 0io f13 i/o 0io f14 i/o 0io g7 i/o 0 io/vref_0 c11 vref 0 io_l01n_0 b17 i/o 0 io_l01p_0 c17 i/o 0 io_l03n_0/vref_0 a18 vref 0 io_l03p_0 a19 i/o 0 io_l04n_0 a17 i/o 0 io_l04p_0 a16 i/o 0 io_l06n_0 a15 i/o 0 io_l06p_0 b15 i/o 0 io_l07n_0 c14 i/o 0 io_l07p_0 d14 i/o 0 io_l09n_0/vref_0 a13 vref 0 io_l09p_0 a14 i/o 0 io_l10n_0 b13 i/o 0 io_l10p_0 c13 i/o 0 io_l11n_0 c12 i/o 0 io_l11p_0 d12 i/o 0 io_l12n_0 e12 i/o 0 io_l12p_0 f12 i/o 0 io_l14n_0/gclk5 g11 gclk 0 io_l14p_0/gclk4 f11 gclk 0 io_l15n_0/gclk7 e10 gclk 0 io_l15p_0/gclk6 e11 gclk 0 io_l17n_0/gclk11 a9 gclk 0 io_l17p_0/gclk10 a10 gclk 0 io_l18n_0 f9 i/o 0 io_l18p_0 e9 i/o 0 io_l20n_0 c9 i/o 0 io_l20p_0 d9 i/o 0 io_l21n_0/vref_0 b8 vref 0 io_l21p_0 b9 i/o 0 io_l23n_0/vref_0 f7 vref 0 io_l23p_0 f8 i/o 0 io_l24n_0 a6 i/o 0 io_l24p_0 a7 i/o 0 io_l26n_0 b5 i/o 0 io_l26p_0 b6 i/o 0 io_l27n_0 d6 i/o 0 io_l27p_0 c6 i/o 0 io_l29n_0/vref_0 c5 vref 0 io_l29p_0 d5 i/o 0 io_l30n_0 a2 i/o 0 io_l30p_0 b2 i/o 0 io_l31n_0/hswap d4 dual 0 io_l31p_0 c4 i/o table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions 54 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 0ip b18input 0 ip e5 input 0 ip_l02n_0 c16 input 0 ip_l02p_0 d16 input 0 ip_l05n_0 d15 input 0 ip_l05p_0 c15 input 0 ip_l08n_0 e14 input 0 ip_l08p_0 e15 input 0 ip_l10n_0 g14 input 0 ip_l10p_0 g13 input 0 ip_l13n_0 b11 input 0 ip_l13p_0 b12 input 0 ip_l16n_0/gclk9 g10 gclk 0 ip_l16p_0/gclk8 h10 gclk 0 ip_l19n_0 g9 input 0 ip_l19p_0 g8 input 0 ip_l22n_0 c8 input 0 ip_l22p_0 d8 input 0 ip_l25n_0 e6 input 0 ip_l25p_0 e7 input 0 ip_l28n_0 a4 input 0 ip_l28p_0 a5 input 0 vcco_0 b4 vcco 0 vcco_0 b10 vcco 0 vcco_0 b16 vcco 0 vcco_0 d7 vcco 0 vcco_0 d13 vcco 0 vcco_0 f10 vcco 1 io_l01n_1/a15 u18 dual 1 io_l01p_1/a16 u17 dual 1 io_l02n_1/a13 t18 dual 1 io_l02p_1/a14 t17 dual 1 io_l03n_1/vref_1 v19 vref 1 io_l03p_1 u19 i/o table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type 1 io_l04n_1 w20 i/o 1 io_l04p_1 v20 i/o 1 io_l05n_1 r18 i/o 1 io_l05p_1 r17 i/o 1 io_l06n_1 t20 i/o 1 io_l06p_1 u20 i/o 1 io_l07n_1 p18 i/o 1 io_l07p_1 p17 i/o 1 io_l08n_1/vref_1 p20 vref 1 io_l08p_1 r20 i/o 1 io_l09n_1 p16 i/o 1 io_l09p_1 n16 i/o 1 io_l10n_1 n19 i/o 1 io_l10p_1 n18 i/o 1 io_l11n_1 n15 i/o 1 io_l11p_1 m15 i/o 1 io_l12n_1/a11 m18 dual 1 io_l12p_1/a12 m17 dual 1 io_l13n_1/vref_1 l19 vref 1 io_l13p_1 m19 i/o 1 io_l14n_1/a9/rhclk1 l16 rhclk/ dual 1 io_l14p_1/a10/rhclk0 m16 rhclk/ dual 1 io_l15n_1/a7/rhclk3/ trdy1 l14 rhclk/ dual 1 io_l15p_1/a8/rhclk2 l15 rhclk/ dual 1 io_l16n_1/a5/rhclk5 k14 rhclk/ dual 1 io_l16p_1/a6/rhclk4/ irdy1 k13 rhclk/ dual 1 io_l17n_1/a3/rhclk7 j20 rhclk/ dual 1 io_l17p_1/a4/rhclk6 k20 rhclk/ dual 1 io_l18n_1/a1 k16 dual 1 io_l18p_1/a2 j16 dual table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 55 advance product specification r 1 io_l19n_1/a0 j13 dual 1 io_l19p_1 j14 i/o 1 io_l20n_1 j17 i/o 1 io_l20p_1 j18 i/o 1 io_l21n_1 h19 i/o 1 io_l21p_1 j19 i/o 1 io_l22n_1 h15 i/o 1 io_l22p_1 h16 i/o 1 io_l23n_1 h18 i/o 1 io_l23p_1 h17 i/o 1 io_l24n_1/vref_1 h20 vref 1 io_l24p_1 g20 i/o 1 io_l25n_1 g16 i/o 1 io_l25p_1 f16 i/o 1 io_l26n_1 f19 i/o 1 io_l26p_1 f20 i/o 1 io_l27n_1 f18 i/o 1 io_l27p_1 f17 i/o 1 io_l28n_1 d20 i/o 1 io_l28p_1 e20 i/o 1 io_l29n_1/ldc0 d18 dual 1 io_l29p_1/hdc e18 dual 1 io_l30n_1/ldc2 c19 dual 1 io_l30p_1/ldc1 c20 dual 1ip b20input 1ip g15input 1ip g18input 1ip h14input 1ip j15input 1ip l18input 1ip m20input 1ip n14input 1ip n20input 1ip p15input table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type 1ip r16input 1ip r19input 1 ip/vref_1 e19 vref 1 ip/vref_1 k18 vref 1 vcco_1 d19 vcco 1 vcco_1 g17 vcco 1 vcco_1 k15 vcco 1 vcco_1 k19 vcco 1 vcco_1 n17 vcco 1 vcco_1 t19 vcco 2io p8 i/o 2io p13 i/o 2io r9 i/o 2io r13 i/o 2io w15 i/o 2io y5 i/o 2io y7 i/o 2io y13 i/o 2 io/d5 n11 dual 2io/m1 t11dual 2 io/vref_2 y3 vref 2 io/vref_2 y17 vref 2 io_l01n_2/init_b v4 dual 2 io_l01p_2/cso_b u4 dual 2 io_l03n_2/mosi/csi_b v5 dual 2 io_l03p_2/dout/busy u5 dual 2 io_l04n_2 y4 i/o 2 io_l04p_2 w4 i/o 2 io_l06n_2 t6 i/o 2 io_l06p_2 t5 i/o 2 io_l07n_2 u7 i/o 2 io_l07p_2 v7 i/o 2 io_l09n_2/vref_2 r7 vref 2 io_l09p_2 t7 i/o table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions 56 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 2 io_l10n_2 v8 i/o 2 io_l10p_2 w8 i/o 2 io_l12n_2 u9 i/o 2 io_l12p_2 v9 i/o 2 io_l13n_2 y8 i/o 2 io_l13p_2 y9 i/o 2 io_l15n_2/d6/gclk13 w10 dual/ gclk 2 io_l15p_2/d7/gclk12 w9 dual/ gclk 2 io_l16n_2/d3/gclk15 p10 dual/ gclk 2 io_l16p_2/d4/gclk14 r10 dual/ gclk 2 io_l18n_2/d1/gclk3 v11 dual/ gclk 2 io_l18p_2/d2/gclk2 v10 dual/ gclk 2 io_l19n_2/din/d0 y12 dual 2 io_l19p_2/m0 y11 dual 2 io_l21n_2 u12 i/o 2 io_l21p_2 v12 i/o 2 io_l22n_2/vref_2 w12 vref 2 io_l22p_2 w13 i/o 2 io_l24n_2 u13 i/o 2 io_l24p_2 v13 i/o 2 io_l25n_2 p14 i/o 2 io_l25p_2 r14 i/o 2 io_l27n_2/a22 y14 dual 2 io_l27p_2/a23 y15 dual 2 io_l28n_2 t15 i/o 2 io_l28p_2 u15 i/o 2 io_l30n_2/a20 v16 dual 2 io_l30p_2/a21 u16 dual 2 io_l31n_2/vs1/a18 y18 dual 2 io_l31p_2/vs2/a19 w18 dual 2 io_l32n_2/cclk w19 dual table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type 2 io_l32p_2/vs0/a17 y19 dual 2ip t16input 2 ip w3 input 2 ip_l02n_2 y2 input 2 ip_l02p_2 w2 input 2 ip_l05n_2 v6 input 2 ip_l05p_2 u6 input 2 ip_l08n_2 y6 input 2 ip_l08p_2 w6 input 2 ip_l11n_2 r8 input 2 ip_l11p_2 t8 input 2 ip_l14n_2/vref_2 t10 vref 2 ip_l14p_2 t9 input 2 ip_l17n_2/m2/gclk1 p12 dual/ gclk 2 ip_l17p_2/rdwr_b/ gclk0 p11 dual/ gclk 2 ip_l20n_2 t12 input 2 ip_l20p_2 r12 input 2 ip_l23n_2/vref_2 t13 vref 2 ip_l23p_2 t14 input 2 ip_l26n_2 v14 input 2 ip_l26p_2 v15 input 2 ip_l29n_2 w16 input 2 ip_l29p_2 y16 input 2 vcco_2 r11 vcco 2 vcco_2 u8 vcco 2 vcco_2 u14 vcco 2 vcco_2 w5 vcco 2 vcco_2 w11 vcco 2 vcco_2 w17 vcco 3 io_l01n_3 d2 i/o 3 io_l01p_3 d3 i/o 3 io_l02n_3/vref_3 e3 vref 3 io_l02p_3 e4 i/o table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 57 advance product specification r 3 io_l03n_3 c1 i/o 3 io_l03p_3 b1 i/o 3 io_l04n_3 e1 i/o 3 io_l04p_3 d1 i/o 3 io_l05n_3 f3 i/o 3 io_l05p_3 f4 i/o 3 io_l06n_3 f1 i/o 3 io_l06p_3 f2 i/o 3 io_l07n_3 g4 i/o 3 io_l07p_3 g3 i/o 3 io_l08n_3 g5 i/o 3 io_l08p_3 h5 i/o 3 io_l09n_3/vref_3 h3 vref 3 io_l09p_3 h2 i/o 3 io_l10n_3 h7 i/o 3 io_l10p_3 h6 i/o 3 io_l11n_3 j4 i/o 3 io_l11p_3 j3 i/o 3 io_l12n_3 j1 i/o 3 io_l12p_3 j2 i/o 3 io_l13n_3 j6 i/o 3 io_l13p_3 k6 i/o 3 io_l14n_3/lhclk1 k2 lhclk 3 io_l14p_3/lhclk0 k3 lhclk 3 io_l15n_3/lhclk3/irdy2 l7 lhclk 3 io_l15p_3/lhclk2 k7 lhclk 3 io_l16n_3/lhclk5 l1 lhclk 3 io_l16p_3/lhclk4/trdy2 m1 lhclk 3 io_l17n_3/lhclk7 l3 lhclk 3 io_l17p_3/lhclk6 m3 lhclk 3 io_l18n_3 m7 i/o 3 io_l18p_3 m8 i/o 3 io_l19n_3 m4 i/o 3 io_l19p_3 m5 i/o table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type 3 io_l20n_3/vref_3 n6 vref 3 io_l20p_3 m6 i/o 3 io_l21n_3 n2 i/o 3 io_l21p_3 n1 i/o 3 io_l22n_3 p7 i/o 3 io_l22p_3 n7 i/o 3 io_l23n_3 n4 i/o 3 io_l23p_3 n3 i/o 3 io_l24n_3 r1 i/o 3 io_l24p_3 p1 i/o 3 io_l25n_3 r5 i/o 3 io_l25p_3 p5 i/o 3 io_l26n_3 t2 i/o 3 io_l26p_3 r2 i/o 3 io_l27n_3 r4 i/o 3 io_l27p_3 r3 i/o 3 io_l28n_3/vref_3 t1 vref 3 io_l28p_3 u1 i/o 3 io_l29n_3 t3 i/o 3 io_l29p_3 u3 i/o 3 io_l30n_3 v1 i/o 3 io_l30p_3 v2 i/o 3 ip f5 input 3ip g1input 3ip g6input 3 ip h1 input 3 ip j5 input 3 ip l5 input 3 ip l8 input 3 ip m2 input 3 ip n5 input 3 ip p3 input 3 ip t4 input 3 ip w1 input table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions 58 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 3 ip/vref_3 k5 vref 3 ip/vref_3 p6 vref 3 vcco_3 e2 vcco 3 vcco_3 h4 vcco 3 vcco_3 l2 vcco 3 vcco_3 l6 vcco 3 vcco_3 p4 vcco 3 vcco_3 u2 vcco gnd gnd a1 gnd gnd gnd a11 gnd gnd gnd a20 gnd gnd gnd b7 gnd gnd gnd b14 gnd gnd gnd c3 gnd gnd gnd c18 gnd gnd gnd d10 gnd gnd gnd f6 gnd gnd gnd f15 gnd gnd gnd g2 gnd gnd gnd g12 gnd gnd gnd g19 gnd gnd gnd h8 gnd gnd gnd j9 gnd gnd gnd j11 gnd gnd gnd k1 gnd gnd gnd k8 gnd gnd gnd k10 gnd gnd gnd k12 gnd gnd gnd k17 gnd gnd gnd l4 gnd gnd gnd l9 gnd gnd gnd l11 gnd gnd gnd l13 gnd gnd gnd l20 gnd table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type gnd gnd m10 gnd gnd gnd m12 gnd gnd gnd n13 gnd gnd gnd p2 gnd gnd gnd p9 gnd gnd gnd p19 gnd gnd gnd r6 gnd gnd gnd r15 gnd gnd gnd u11 gnd gnd gnd v3 gnd gnd gnd v18 gnd gnd gnd w7 gnd gnd gnd w14 gnd gnd gnd y1 gnd gnd gnd y10 gnd gnd gnd y20 gnd vccaux done v17 config vccaux prog_b c2 config vccaux tck d17 jtag vccaux tdi b3 jtag vccaux tdo b19 jtag vccaux tms e17 jtag vccaux vccaux d11 vccaux vccaux vccaux h12 vccaux vccaux vccaux j7 vccaux vccaux vccaux k4 vccaux vccaux vccaux l17 vccaux vccaux vccaux m14 vccaux vccaux vccaux n9 vccaux vccaux vccaux u10 vccaux vccint vccint h9 vccint vccint vccint h11 vccint vccint vccint h13 vccint vccint vccint j8 vccint table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 59 advance product specification r user i/os by bank ta b l e 3 0 indicates how the 304 available user-i/o pins are distributed between the four i/o banks on the fg400 pack- age. footprint migration differences the xc3s1200e and xc3s1600e fpgas have identical footprints in the fg400 package. designs can migrate between the xc3s1200e and xc3s1600e fpgas without further consideration. vccint vccint j10 vccint vccint vccint j12 vccint vccint vccint k9 vccint vccint vccint k11 vccint vccint vccint l10 vccint vccint vccint l12 vccint vccint vccint m9 vccint vccint vccint m11 vccint table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type vccint vccint m13 vccint vccint vccint n8 vccint vccint vccint n10 vccint vccint vccint n12 vccint table 29: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type table 30: user i/os per bank for the xc3s250e and xc3s500e in the fg400 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 78 43 20 1 6 8 right 1 74 35 12 21 6 0 bottom 2 78 30 18 24 6 0 left 3 74 48 12 0 6 8 total 304 156 62 46 24 16 pinout descriptions 60 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r fg400 footprint left half of package (top view) 156 i/o: unrestricted, general-purpose user i/o 62 input: user i/o or reference resistor input for bank 46 dual: configuration pin, then possible user i/o 24 vref: user i/o or input voltage reference for bank 16 gclk: user i/o, input, or clock buffer input 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 42 gnd: ground 24 vcco: output voltage supply for bank 16 vccint: internal core supply voltage (+1.2v) 8 vccaux: auxiliary supply voltage (+2.5v) 0 n.c.: not connected figure 9: fg400 package footprint (top view) 12345678 10 a gnd i/o l30n_0 i/o input l28n_0 input l28p_0 i/o l24n_0 i/o l24p_0 i/o i/o l17n_0 gclk11 i/o l17p_0 gclk10 b i/o l03p_3 i/o l30p_0 tdi vcco_0 i/o l26n_0 i/o l26p_0 gnd i/o l21n_0 vref_0 i/o l21p_0 vcco_0 c i/o l03n_3 prog_b gnd i/o l31p_0 i/o l29n_0 vref_0 i/o l27p_0 i/o input l22n_0 i/o l20n_0 i/o d i/o l04p_3 i/o l01n_3 i/o l01p_3 i/o l31n_0 hswap i/o l29p_0 i/o l27n_0 vcco_0 input l22p_0 i/o l20p_0 gnd e i/o l04n_3 vcco_3 i/o l02n_3 vref_3 i/o l02p_3 input input l25n_0 input l25p_0 i/o i/o l18p_0 i/o l15n_0 gclk7 f i/o l06n_3 i/o l06p_3 i/o l05n_3 i/o l05p_3 input gnd i/o l23n_0 vref_0 i/o l23p_0 i/o l18n_0 vcco_0 g input gnd i/o l07p_3 i/o l07n_3 i/o l08n_3 input i/o input l19p_0 input l19n_0 input l16n_0 gclk9 h input i/o l09p_3 i/o l09n_3 vref_3 vcco_3 i/o l08p_3 i/o l10p_3 i/o l10n_3 gnd vccint input l16p_0 gclk8 j i/o l12n_3 i/o l12p_3 i/o l11p_3 i/o l11n_3 input i/o l13n_3 vccaux vccint gnd vccint k gnd i/o l14n_3 lhclk1 i/o l14p_3 lhclk0 vccaux input vref_3 i/o l13p_3 i/o l15p_3 lhclk2 gnd vccint gnd l i/o l16n_3 lhclk5 vcco_3 i/o l17n_3 lhclk7 gnd input vcco_3 i/o l15n_3 lhclk3 irdy2 input gnd vccint m i/o l16p_3 lhclk4 t rdy2 input i/o l17p_3 lhclk6 i/o l19n_3 i/o l19p_3 i/o l20p_3 i/o l18n_3 i/o l18p_3 vccint gnd n i/o l21p_3 i/o l21n_3 i/o l23p_3 i/o l23n_3 input i/o l20n_3 vref_3 i/o l22p_3 vccint vccaux vccint p i/o l24p_3 gnd input vcco_3 i/o l25p_3 input vref_3 i/o l22n_3 i/o gnd r i/o l24n_3 i/o l26p_3 i/o l27p_3 i/o l27n_3 i/o l25n_3 gnd i/o l09n_2 vref_2 input l11n_2 i/o t i/o l28n_3 vref_3 i/o l26n_3 i/o l29n_3 input i/o l06p_2 i/o l06n_2 i/o l09p_2 input l11p_2 input l14p_2 input l14n_2 vref_2 u i/o l28p_3 vcco_3 i/o l29p_3 i/o l01p_2 cso_b i/o l03p_2 dout busy input l05p_2 i/o l07n_2 vcco_2 i/o l12n_2 vccaux v i/o l30n_3 i/o l30p_3 gnd i/o l01n_2 init_b input l05n_2 i/o l07p_2 i/o l10n_2 i/o l12p_2 w input input l02p_2 input i/o l04p_2 vcco_2 input l08p_2 gnd i/o l10p_2 i/o y gnd input l02n_2 i/o vref_2 i/o l04n_2 i/o input l08n_2 i/o i/o l13n_2 i/o l13p_2 gnd bank 0 bank 3 bank 2 gclk13 l15n_2 d6 gclk2 d2 l18p_2 i/o gclk12 l15p_2 d7 i/o gclk14 d4 l16p_2 i/o lk15 d3 l16n_2 i/o gc csi_b mosi l03n_2 i/o 9 ds312-4_08_031105 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 61 advance product specification r right half of package (top view) 11 12 13 14 15 16 17 18 19 20 gnd i/o i/o l09n_0 vref_0 i/o l09p_0 i/o l06n_0 i/o l04p_0 i/o l04n_0 i/o l03n_0 vref_0 i/o l03p_0 gnd a input l13n_0 input l13p_0 i/o l10n_0 gnd i/o l06p_0 vcco_0 i/o l01n_0 input tdo input b i/o vref_0 i/o l11n_0 i/o l10p_0 i/o l07n_0 input l05p_0 input l02n_0 i/o l01p_0 gnd i/o l30n_1 ldc2 i/o l30p_1 ldc1 c vccaux i/o l11p_0 vcco_0 i/o l07p_0 input l05n_0 input l02p_0 tck i/o l29n_1 ldc0 vcco_1 i/o l28n_1 d i/o l15p_0 gclk6 i/o l12n_0 i/o input l08n_0 input l08p_0 i/o tms i/o l29p_1 hdc input vref_1 i/o l28p_1 e i/o l14p_0 gclk4 i/o l12p_0 i/o i/o gnd i/o l25p_1 i/o l27p_1 i/o l27n_1 i/o l26n_1 i/o l26p_1 f i/o l14n_0 gclk5 gnd input l10p_0 input l10n_0 input i/o l25n_1 vcco_1 input gnd i/o l24p_1 g vccint vccaux vccint input i/o l22n_1 i/o l22p_1 i/o l23p_1 i/o l23n_1 i/o l21n_1 i/o l24n_1 vref_1 h gnd vccint i/o l19n_1 a0 i/o l19p_1 input i/o l18p_1 a2 i/o l20n_1 i/o l20p_1 i/o l21p_1 j vccint gnd vcco_1 i/o l18n_1 a1 gnd input vref_1 vcco_1 k gnd vccint gnd vccaux input i/o l13n_1 vref_1 gnd l vccint gnd vccint vccaux i/o l11p_1 i/o i/o l12p_1 a12 i/o l12n_1 a11 i/o l13p_1 input m i/o d5 vccint gnd input i/o l11n_1 i/o l09p_1 vcco_1 i/o l10p_1 i/o l10n_1 input n i/o i/o l25n_2 input i/o l09n_1 i/o l07p_1 i/o l07n_1 gnd i/o l08n_1 vref_1 p vcco_2 input l20p_2 i/o i/o l25p_2 gnd input i/o l05p_1 i/o l05n_1 input i/o l08p_1 r i/o m1 input l20n_2 input l23n_2 vref_2 input l23p_2 i/o l28n_2 input i/o l02p_1 a14 i/o l02n_1 a13 vcco_1 i/o l06n_1 t gnd i/o l21n_2 i/o l24n_2 vcco_2 i/o l28p_2 i/o l30p_2 a21 i/o l01p_1 a16 i/o l01n_1 a15 i/o l03p_1 i/o l06p_1 u i/o l21p_2 i/o l24p_2 input l26n_2 input l26p_2 i/o l30n_2 a20 done gnd i/o l03n_1 vref_1 i/o l04p_1 v vcco_2 i/o l22n_2 vref_2 i/o l22p_2 gnd i/o input l29n_2 vcco_2 i/o l31p_2 vs2 a19 i/o l32n_2 cclk i/o l04n_1 w i/o l19p_2 m0 i/o l19n_2 din d0 i/o i/o l27n_2 a22 i/o l27p_2 a23 input l29p_2 i/o vref_2 i/o l31n_2 vs1 a18 i/o l32p_2 vs0 a17 gnd y bank 1 bank 2 bank 0 i/o l18n_2 d1 gc lk3 input l17p_2 rdwr_b gclk0 input l17n_2 m2 gclk1 rh c lk1 l14n_1 a9 i/o c rh lk 0 a10 l14p_1 c i/o l16p_1 a6 irdy1 rh lk4 l16n_1 a5 i/o rhclk 5 rhclk3 l15n_1 trdy1 a7 i/o i/o l15p_1 a 8 rhclk2 rhclk 6 a4 l17p_1 i/o rhclk7 a3 l17n_1 i/o ds312-4_09_031105 pinout descriptions 62 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r fg484: 484-ball fine-pitch ball grid array the 484-ball fine-pitch ball grid array, fg484, supports the xc3s1600e fpga. ta b l e 3 1 lists all the fg484 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web- site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip . pinout table table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type 0 io b6 i/o 0 io b13 i/o 0 io c5 i/o 0 io c14 i/o 0 io e16 i/o 0 io f9 i/o 0 io f16 i/o 0 io g8 i/o 0 io h10 i/o 0 io h15 i/o 0 io j11 i/o 0 io/vref_0 g12 vref 0 io_l01n_0 c18 i/o 0 io_l01p_0 c19 i/o 0 io_l03n_0/vref_0 a20 vref 0 io_l03p_0 a21 i/o 0 io_l04n_0 a19 i/o 0 io_l04p_0 a18 i/o 0 io_l06n_0 c16 i/o 0 io_l06p_0 d16 i/o 0 io_l07n_0 a16 i/o 0 io_l07p_0 a17 i/o 0 io_l09n_0/vref_0 b15 vref 0 io_l09p_0 c15 i/o 0 io_l10n_0 g15 i/o 0 io_l10p_0 f15 i/o 0 io_l11n_0 d14 i/o 0 io_l11p_0 e14 i/o 0 io_l12n_0/vref_0 a14 vref 0 io_l12p_0 a15 i/o 0 io_l13n_0 h14 i/o 0 io_l13p_0 g14 i/o 0 io_l15n_0 g13 i/o 0 io_l15p_0 f13 i/o 0 io_l16n_0 j13 i/o 0 io_l16p_0 h13 i/o 0 io_l18n_0/gclk5 e12 gclk 0 io_l18p_0/gclk4 f12 gclk 0 io_l19n_0/gclk7 c12 gclk 0 io_l19p_0/gclk6 b12 gclk 0 io_l21n_0/gclk11 b11 gclk 0 io_l21p_0/gclk10 c11 gclk 0 io_l22n_0 d11 i/o 0 io_l22p_0 e11 i/o 0 io_l24n_0 a9 i/o 0 io_l24p_0 a10 i/o 0 io_l25n_0/vref_0 d10 vref 0 io_l25p_0 c10 i/o 0 io_l27n_0 h8 i/o 0 io_l27p_0 h9 i/o 0 io_l28n_0 c9 i/o 0 io_l28p_0 b9 i/o 0 io_l29n_0 e9 i/o 0 io_l29p_0 d9 i/o 0 io_l30n_0 b8 i/o 0 io_l30p_0 a8 i/o 0 io_l32n_0/vref_0 f7 vref 0 io_l32p_0 f8 i/o 0 io_l33n_0 a6 i/o table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 63 advance product specification r 0 io_l33p_0 a7 i/o 0 io_l35n_0 a4 i/o 0 io_l35p_0 a5 i/o 0 io_l36n_0 e7 i/o 0 io_l36p_0 d7 i/o 0 io_l38n_0/vref_0 d6 vref 0 io_l38p_0 d5 i/o 0 io_l39n_0 b4 i/o 0 io_l39p_0 b3 i/o 0 io_l40n_0/hswap d4 dual 0 io_l40p_0 c4 i/o 0 ip b19 input 0 ip e6 input 0 ip_l02n_0 d17 input 0 ip_l02p_0 d18 input 0 ip_l05n_0 c17 input 0 ip_l05p_0 b17 input 0 ip_l08n_0 e15 input 0 ip_l08p_0 d15 input 0 ip_l14n_0 d13 input 0 ip_l14p_0 c13 input 0 ip_l17n_0 a12 input 0 ip_l17p_0 a13 input 0 ip_l20n_0/gclk9 h11 gclk 0 ip_l20p_0/gclk8 h12 gclk 0 ip_l23n_0 f10 input 0 ip_l23p_0 f11 input 0 ip_l26n_0 g9 input 0 ip_l26p_0 g10 input 0 ip_l31n_0 c8 input 0 ip_l31p_0 d8 input 0 ip_l34n_0 c7 input 0 ip_l34p_0 c6 input 0 ip_l37n_0 a3 input 0 ip_l37p_0 a2 input table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type 0 vcco_0 b5 vcco 0 vcco_0 b10 vcco 0 vcco_0 b14 vcco 0 vcco_0 b18 vcco 0 vcco_0 e8 vcco 0 vcco_0 f14 vcco 0 vcco_0 g11 vcco 1 io_l01n_1/a15 y22 dual 1 io_l01p_1/a16 aa22 dual 1 io_l02n_1/a13 w21 dual 1 io_l02p_1/a14 y21 dual 1 io_l03n_1/vref_1 w20 vref 1 io_l03p_1 v20 i/o 1 io_l04n_1 u19 i/o 1 io_l04p_1 v19 i/o 1 io_l05n_1 v22 i/o 1 io_l05p_1 w22 i/o 1 io_l06n_1 t19 i/o 1 io_l06p_1 t18 i/o 1 io_l07n_1/vref_1 u20 vref 1 io_l07p_1 u21 i/o 1 io_l08n_1 t22 i/o 1 io_l08p_1 u22 i/o 1 io_l09n_1 r19 i/o 1 io_l09p_1 r18 i/o 1 io_l10n_1 r16 i/o 1 io_l10p_1 t16 i/o 1 io_l11n_1 r21 i/o 1 io_l11p_1 r20 i/o 1 io_l12n_1/vref_1 p18 vref 1 io_l12p_1 p17 i/o 1 io_l13n_1 p22 i/o 1 io_l13p_1 r22 i/o 1 io_l14n_1 p15 i/o 1 io_l14p_1 p16 i/o table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type pinout descriptions 64 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 1 io_l15n_1 n18 i/o 1 io_l15p_1 n19 i/o 1 io_l16n_1/a11 n16 dual 1 io_l16p_1/a12 n17 dual 1 io_l17n_1/vref_1 m20 vref 1 io_l17p_1 n20 i/o 1 io_l18n_1/a9/rhclk1 m22 rhclk/ dual 1 io_l18p_1/a10/rhclk0 n22 rhclk/ dual 1 io_l19n_1/a7/rhclk3/ trdy1 m16 rhclk/ dual 1 io_l19p_1/a8/rhclk2 m15 rhclk/ dual 1 io_l20n_1/a5/rhclk5 l21 rhclk/ dual 1 io_l20p_1/a6/rhclk4/ irdy1 l20 rhclk/ dual 1 io_l21n_1/a3/rhclk7 l19 rhclk/ dual 1 io_l21p_1/a4/rhclk6 l18 rhclk/ dual 1 io_l22n_1/a1 k22 dual 1 io_l22p_1/a2 l22 dual 1 io_l23n_1/a0 k17 dual 1 io_l23p_1 k16 i/o 1 io_l24n_1 k19 i/o 1 io_l24p_1 k18 i/o 1 io_l25n_1 k15 i/o 1 io_l25p_1 j15 i/o 1 io_l26n_1 j20 i/o 1 io_l26p_1 j21 i/o 1 io_l27n_1 j17 i/o 1 io_l27p_1 j18 i/o 1 io_l28n_1/vref_1 h21 vref 1 io_l28p_1 h22 i/o 1 io_l29n_1 h20 i/o 1 io_l29p_1 h19 i/o table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type 1 io_l30n_1 h17 i/o 1 io_l30p_1 g17 i/o 1 io_l31n_1 f22 i/o 1 io_l31p_1 g22 i/o 1 io_l32n_1 f20 i/o 1 io_l32p_1 g20 i/o 1 io_l33n_1 g18 i/o 1 io_l33p_1 g19 i/o 1 io_l34n_1 d22 i/o 1 io_l34p_1 e22 i/o 1 io_l35n_1 f19 i/o 1 io_l35p_1 f18 i/o 1 io_l36n_1 e20 i/o 1 io_l36p_1 e19 i/o 1 io_l37n_1/ldc0 c21 dual 1 io_l37p_1/hdc c22 dual 1 io_l38n_1/ldc2 b21 dual 1 io_l38p_1/ldc1 b22 dual 1 ip d20 input 1 ip f21 input 1 ip g16 input 1 ip h16 input 1 ip j16 input 1 ip j22 input 1 ip k20 input 1 ip l15 input 1 ip m18 input 1 ip n15 input 1 ip n21 input 1 ip p20 input 1 ip r15 input 1 ip t17 input 1 ip t20 input 1 ip u18 input 1 ip/vref_1 d21 vref table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 65 advance product specification r 1 ip/vref_1 l17 vref 1 vcco_1 e21 vcco 1 vcco_1 h18 vcco 1 vcco_1 k21 vcco 1 vcco_1 l16 vcco 1 vcco_1 p21 vcco 1 vcco_1 r17 vcco 1 vcco_1 v21 vcco 2 io y8 i/o 2 io y9 i/o 2 io aa10 i/o 2 io ab5 i/o 2 io ab13 i/o 2 io ab14 i/o 2 io ab16 i/o 2 io ab18 i/o 2 io/d5 ab11 dual 2 io/m1 aa12 dual 2 io/vref_2 ab4 vref 2 io/vref_2 ab21 vref 2 io_l01n_2/init_b ab3 dual 2 io_l01p_2/cso_b aa3 dual 2 io_l03n_2/mosi/csi_b y5 dual 2 io_l03p_2/dout/busy w5 dual 2 io_l04n_2 w6 i/o 2 io_l04p_2 v6 i/o 2 io_l06n_2 w7 i/o 2 io_l06p_2 y7 i/o 2 io_l07n_2 u7 i/o 2 io_l07p_2 v7 i/o 2 io_l09n_2/vref_2 v8 vref 2 io_l09p_2 w8 i/o 2 io_l10n_2 t8 i/o 2 io_l10p_2 u8 i/o 2 io_l11n_2 ab8 i/o table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type 2 io_l11p_2 aa8 i/o 2 io_l12n_2 w9 i/o 2 io_l12p_2 v9 i/o 2 io_l13n_2/vref_2 r9 vref 2 io_l13p_2 t9 i/o 2 io_l14n_2 ab9 i/o 2 io_l14p_2 ab10 i/o 2 io_l16n_2 u10 i/o 2 io_l16p_2 t10 i/o 2 io_l17n_2 r10 i/o 2 io_l17p_2 p10 i/o 2 io_l19n_2/d6/gclk13 u11 dual/ gclk 2 io_l19p_2/d7/gclk12 v11 dual/ gclk 2 io_l20n_2/d3/gclk15 t11 dual/ gclk 2 io_l20p_2/d4/gclk14 r11 dual/ gclk 2 io_l22n_2/d1/gclk3 w12 dual/ gclk 2 io_l22p_2/d2/gclk2 y12 dual/ gclk 2 io_l23n_2/din/d0 u12 dual 2 io_l23p_2/m0 v12 dual 2 io_l25n_2 y13 i/o 2 io_l25p_2 w13 i/o 2 io_l26n_2/vref_2 u14 vref 2 io_l26p_2 u13 i/o 2 io_l27n_2 t14 i/o 2 io_l27p_2 r14 i/o 2 io_l28n_2 y14 i/o 2 io_l28p_2 aa14 i/o 2 io_l29n_2 w14 i/o 2 io_l29p_2 v14 i/o 2 io_l30n_2 ab15 i/o 2 io_l30p_2 aa15 i/o table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type pinout descriptions 66 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 2 io_l32n_2 w15 i/o 2 io_l32p_2 y15 i/o 2 io_l33n_2 u16 i/o 2 io_l33p_2 v16 i/o 2 io_l35n_2/a22 ab17 dual 2 io_l35p_2/a23 aa17 dual 2 io_l36n_2 w17 i/o 2 io_l36p_2 y17 i/o 2 io_l38n_2/a20 y18 dual 2 io_l38p_2/a21 w18 dual 2 io_l39n_2/vs1/a18 aa20 dual 2 io_l39p_2/vs2/a19 ab20 dual 2 io_l40n_2/cclk w19 dual 2 io_l40p_2/vs0/a17 y19 dual 2 ip v17 input 2 ip ab2 input 2 ip_l02n_2 aa4 input 2 ip_l02p_2 y4 input 2 ip_l05n_2 y6 input 2 ip_l05p_2 aa6 input 2 ip_l08n_2 ab7 input 2 ip_l08p_2 ab6 input 2 ip_l15n_2 y10 input 2 ip_l15p_2 w10 input 2 ip_l18n_2/vref_2 aa11 vref 2 ip_l18p_2 y11 input 2 ip_l21n_2/m2/gclk1 p12 dual/ gclk 2 ip_l21p_2/rdwr_b/ gclk0 r12 dual/ gclk 2 ip_l24n_2 r13 input 2 ip_l24p_2 t13 input 2 ip_l31n_2/vref_2 t15 vref 2 ip_l31p_2 u15 input 2 ip_l34n_2 y16 input 2 ip_l34p_2 w16 input table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type 2 ip_l37n_2 aa19 input 2 ip_l37p_2 ab19 input 2 vcco_2 t12 vcco 2 vcco_2 u9 vcco 2 vcco_2 v15 vcco 2 vcco_2 aa5 vcco 2 vcco_2 aa9 vcco 2 vcco_2 aa13 vcco 2 vcco_2 aa18 vcco 3 io_l01n_3 c1 i/o 3 io_l01p_3 c2 i/o 3 io_l02n_3/vref_3 d2 vref 3 io_l02p_3 d3 i/o 3 io_l03n_3 e3 i/o 3 io_l03p_3 e4 i/o 3 io_l04n_3 e1 i/o 3 io_l04p_3 d1 i/o 3 io_l05n_3 f4 i/o 3 io_l05p_3 f3 i/o 3 io_l06n_3 g5 i/o 3 io_l06p_3 g4 i/o 3 io_l07n_3 f1 i/o 3 io_l07p_3 g1 i/o 3 io_l08n_3/vref_3 g6 vref 3 io_l08p_3 g7 i/o 3 io_l09n_3 h4 i/o 3 io_l09p_3 h5 i/o 3 io_l10n_3 h2 i/o 3 io_l10p_3 h3 i/o 3 io_l11n_3 h1 i/o 3 io_l11p_3 j1 i/o 3 io_l12n_3 j6 i/o 3 io_l12p_3 j5 i/o 3 io_l13n_3/vref_3 j3 vref 3 io_l13p_3 k3 i/o table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 67 advance product specification r 3 io_l14n_3 j8 i/o 3 io_l14p_3 k8 i/o 3 io_l15n_3 k4 i/o 3 io_l15p_3 k5 i/o 3 io_l16n_3 k1 i/o 3 io_l16p_3 l1 i/o 3 io_l17n_3 l7 i/o 3 io_l17p_3 k7 i/o 3 io_l18n_3/lhclk1 l5 lhclk 3 io_l18p_3/lhclk0 m5 lhclk 3 io_l19n_3/lhclk3/irdy2 m8 lhclk 3 io_l19p_3/lhclk2 l8 lhclk 3 io_l20n_3/lhclk5 n1 lhclk 3 io_l20p_3/lhclk4/trdy2 m1 lhclk 3 io_l21n_3/lhclk7 m4 lhclk 3 io_l21p_3/lhclk6 m3 lhclk 3 io_l22n_3 n6 i/o 3 io_l22p_3 n7 i/o 3 io_l23n_3 p8 i/o 3 io_l23p_3 n8 i/o 3 io_l24n_3/vref_3 n4 vref 3 io_l24p_3 n5 i/o 3 io_l25n_3 p2 i/o 3 io_l25p_3 p1 i/o 3 io_l26n_3 r7 i/o 3 io_l26p_3 p7 i/o 3 io_l27n_3 p6 i/o 3 io_l27p_3 p5 i/o 3 io_l28n_3 r2 i/o 3 io_l28p_3 r1 i/o 3 io_l29n_3 r3 i/o 3 io_l29p_3 r4 i/o 3 io_l30n_3 t6 i/o 3 io_l30p_3 r6 i/o 3 io_l31n_3 u2 i/o table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type 3 io_l31p_3 u1 i/o 3 io_l32n_3 t4 i/o 3 io_l32p_3 t5 i/o 3 io_l33n_3 w1 i/o 3 io_l33p_3 v1 i/o 3 io_l34n_3 u4 i/o 3 io_l34p_3 u3 i/o 3 io_l35n_3 v4 i/o 3 io_l35p_3 v3 i/o 3 io_l36n_3/vref_3 w3 vref 3 io_l36p_3 w2 i/o 3 io_l37n_3 y2 i/o 3 io_l37p_3 y1 i/o 3 io_l38n_3 aa1 i/o 3 io_l38p_3 aa2 i/o 3 ip f2 input 3 ip f5 input 3 ip g3 input 3 ip h7 input 3 ip j7 input 3 ip k2 input 3 ip k6 input 3 ip m2 input 3 ip m6 input 3 ip n3 input 3 ip p3 input 3 ip r8 input 3 ip t1 input 3 ip t7 input 3 ip u5 input 3 ip w4 input 3 ip/vref_3 l3 vref 3 ip/vref_3 t3 vref 3 vcco_3 e2 vcco 3 vcco_3 h6 vcco table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type pinout descriptions 68 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r 3 vcco_3 j2 vcco 3 vcco_3 m7 vcco 3 vcco_3 n2 vcco 3 vcco_3 r5 vcco 3 vcco_3 v2 vcco gnd gnd a1 gnd gnd gnd a11 gnd gnd gnd a22 gnd gnd gnd b7 gnd gnd gnd b16 gnd gnd gnd c3 gnd gnd gnd c20 gnd gnd gnd e10 gnd gnd gnd e13 gnd gnd gnd f6 gnd gnd gnd f17 gnd gnd gnd g2 gnd gnd gnd g21 gnd gnd gnd j4 gnd gnd gnd j9 gnd gnd gnd j12 gnd gnd gnd j14 gnd gnd gnd j19 gnd gnd gnd k10 gnd gnd gnd k12 gnd gnd gnd l2 gnd gnd gnd l6 gnd gnd gnd l9 gnd gnd gnd l13 gnd gnd gnd m10 gnd gnd gnd m14 gnd gnd gnd m17 gnd gnd gnd m21 gnd gnd gnd n11 gnd gnd gnd n13 gnd table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type gnd gnd p4 gnd gnd gnd p9 gnd gnd gnd p11 gnd gnd gnd p14 gnd gnd gnd p19 gnd gnd gnd t2 gnd gnd gnd t21 gnd gnd gnd u6 gnd gnd gnd u17 gnd gnd gnd v10 gnd gnd gnd v13 gnd gnd gnd y3 gnd gnd gnd y20 gnd gnd gnd aa7 gnd gnd gnd aa16 gnd gnd gnd ab1 gnd gnd gnd ab12 gnd gnd gnd ab22 gnd vccaux done aa21 config vccaux prog_b b1 config vccaux tck e17 jtag vccaux tdi b2 jtag vccaux tdo b20 jtag vccaux tms d19 jtag vccaux vccaux d12 vccaux vccaux vccaux e5 vccaux vccaux vccaux e18 vccaux vccaux vccaux k14 vccaux vccaux vccaux l4 vccaux vccaux vccaux m19 vccaux vccaux vccaux n9 vccaux vccaux vccaux v5 vccaux vccaux vccaux v18 vccaux vccaux vccaux w11 vccaux vccint vccint j10 vccint table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 69 advance product specification r user i/os by bank table 32 indicates how the 304 available user-i/o pins are distributed between the four i/o banks on the fg484 pack- age. footprint migration differences the xc3s1600e fpga is the only spartan-3e device offered in the fg484 package. vccint vccint k9 vccint vccint vccint k11 vccint vccint vccint k13 vccint vccint vccint l10 vccint vccint vccint l11 vccint vccint vccint l12 vccint vccint vccint l14 vccint vccint vccint m9 vccint vccint vccint m11 vccint vccint vccint m12 vccint table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type vccint vccint m13 vccint vccint vccint n10 vccint vccint vccint n12 vccint vccint vccint n14 vccint vccint vccint p13 vccint table 31: fg484 package pinout bank xc3s1600e pin name fg484 ball type table 32: user i/os per bank for the xc3s1600e in the fg484 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref gclk to p 0 94 56 22 1 7 8 right 1 94 50 16 21 7 0 bottom 2 94 45 18 24 7 0 left 3 94 63 16 0 7 8 total 376 214 72 46 28 16 pinout descriptions 70 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r fg484 footprint left half of package (top view) 214 i/o: unrestricted, general-purpose user i/o 72 input: user i/o or reference resistor input for bank 46 dual: configuration pin, then possible user i/o 28 vref: user i/o or input voltage reference for bank 16 gclk: user i/o, input, or clock buffer input 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 48 gnd: ground 28 vcco: output voltage supply for bank 16 vccint: internal core supply voltage (+1.2v) 10 vccaux: auxiliary supply voltage (+2.5v) 0 n.c.: not connected figure 10: fg484 package footprint (top view) 1234567891011 a gnd input l37p_0 input l37n_0 i/o l35n_0 i/o l35p_0 i/o l33n_0 i/o l33p_0 i/o l30p_0 i/o l24n_0 i/o l24p_0 gnd b prog_b tdi i/o l39p_0 i/o l39n_0 vcco_0 i/o gnd i/o l30n_0 i/o l28p_0 vcco_0 i/o l21n_0 gclk11 c i/o l01n_3 i/o l01p_3 gnd i/o l40p_0 i/o input l34p_0 input l34n_0 input l31n_0 i/o l28n_0 i/o l25p_0 i/o l21p_0 gclk10 d i/o l04p_3 i/o l02n_3 vref_3 i/o l02p_3 i/o l40n_0 hswap i/o l38p_0 i/o l38n_0 vref_0 i/o l36p_0 input l31p_0 i/o l29p_0 i/o l25n_0 vref_0 i/o l22n_0 e i/o l04n_3 vcco_3 i/o l03n_3 i/o l03p_3 vccaux input i/o l36n_0 vcco_0 i/o l29n_0 gnd i/o l22p_0 f i/o l07n_3 input i/o l05p_3 i/o l05n_3 input gnd i/o l32n_0 vref_0 i/o l32p_0 i/o input l23n_0 input l23p_0 g i/o l07p_3 gnd input i/o l06p_3 i/o l06n_3 i/o l08n_3 vref_3 i/o l08p_3 i/o input l26n_0 input l26p_0 vcco_0 h i/o l11n_3 i/o l10n_3 i/o l10p_3 i/o l09n_3 i/o l09p_3 vcco_3 input i/o l27n_0 i/o l27p_0 i/o input l20n_0 gclk9 j i/o l11p_3 vcco_3 i/o l13n_3 vref_3 gnd i/o l12p_3 i/o l12n_3 input i/o l14n_3 gnd vccint i/o k i/o l16n_3 input i/o l13p_3 i/o l15n_3 i/o l15p_3 input i/o l17p_3 i/o l14p_3 vccint gnd vccint l i/o l16p_3 gnd input vref_3 vccaux i/o l18n_3 lhclk1 gnd i/o l17n_3 i/o l19p_3 lhclk2 gnd vccint vccint m i/o l20p_3 lhclk4 trdy2 input i/o l21p_3 lhclk6 i/o l21n_3 lhclk7 i/o l18p_3 lhclk0 input vcco_3 i/o l19n_3 lhclk3 irdy2 vccint gnd vccint n i/o l20n_3 lhclk5 vcco_3 input i/o l24n_3 vref_3 i/o l24p_3 i/o l22n_3 i/o l22p_3 i/o l23p_3 vccaux vccint gnd p i/o l25p_3 i/o l25n_3 input gnd i/o l27p_3 i/o l27n_3 i/o l26p_3 i/o l23n_3 gnd i/o l17p_2 gnd r i/o l28p_3 i/o l28n_3 i/o l29n_3 i/o l29p_3 vcco_3 i/o l30p_3 i/o l26n_3 input i/o l13n_2 vref_2 i/o l17n_2 t input gnd input vref_3 i/o l32n_3 i/o l32p_3 i/o l30n_3 input i/o l10n_2 i/o l13p_2 i/o l16p_2 u i/o l31p_3 i/o l31n_3 i/o l34p_3 i/o l34n_3 input gnd i/o l07n_2 i/o l10p_2 vcco_2 i/o l16n_2 v i/o l33p_3 vcco_3 i/o l35p_3 i/o l35n_3 vccaux i/o l04p_2 i/o l07p_2 i/o l09n_2 vref_2 i/o l12p_2 gnd w i/o l33n_3 i/o l36p_3 i/o l36n_3 vref_3 input i/o l03p_2 dout busy i/o l04n_2 i/o l06n_2 i/o l09p_2 i/o l12n_2 input l15p_2 vccaux y i/o l37p_3 i/o l37n_3 gnd input l02p_2 i/o l03n_2 input l05n_2 i/o l06p_2 i/o i/o input l15n_2 input l18p_2 a a i/o l38n_3 i/o l38p_3 i/o l01p_2 cso_b input l02n_2 vcco_2 input l05p_2 gnd i/o l11p_2 vcco_2 i/o input l18n_2 vref_2 a b gnd input i/o l01n_2 init_b i/o vref_2 i/o input l08p_2 input l08n_2 i/o l11n_2 i/o l14n_2 i/o l14p_2 i/o d5 bank 3 bank 0 bank 2 csi_b mosi gclk12 d7 l19p_2 i/o gclk13 d6 l19n_2 i/o gclk15 d3 l20n_2 i/o gclk14 d4 l20p_2 i/o ds312_10_031105 pinout descriptions ds312-4 (v1.1) march 21, 2005 www.xilinx.com 71 advance product specification r right half of package (top view) 12 13 14 15 16 17 18 19 20 21 22 input l17n_0 input l17p_0 i/o l12n_0 vref_0 i/o l12p_0 i/o l07n_0 i/o l07p_0 i/o l04p_0 i/o l04n_0 i/o l03n_0 vref_0 i/o l03p_0 gnd a i/o l19p_0 gclk6 i/o vcco_0 i/o l09n_0 vref_0 gnd input l05p_0 vcco_0 input tdo i/o l38n_1 ldc2 i/o l38p_1 ldc1 b i/o l19n_0 gclk7 input l14p_0 i/o i/o l09p_0 i/o l06n_0 input l05n_0 i/o l01n_0 i/o l01p_0 gnd i/o l37n_1 ldc0 i/o l37p_1 hdc c vccaux input l14n_0 i/o l11n_0 input l08p_0 i/o l06p_0 input l02n_0 input l02p_0 tms input input vref_1 i/o l34n_1 d i/o l18n_0 gclk5 gnd i/o l11p_0 input l08n_0 i/o tck vccaux i/o l36p_1 i/o l36n_1 vcco_1 i/o l34p_1 e i/o l18p_0 gclk4 i/o l15p_0 vcco_0 i/o l10p_0 i/o gnd i/o l35p_1 i/o l35n_1 i/o l32n_1 input i/o l31n_1 f i/o vref_0 i/o l15n_0 i/o l13p_0 i/o l10n_0 input i/o l30p_1 i/o l33n_1 i/o l33p_1 i/o l32p_1 gnd i/o l31p_1 g input l20p_0 gclk8 i/o l16p_0 i/o l13n_0 i/o input i/o l30n_1 vcco_1 i/o l29p_1 i/o l29n_1 i/o l28n_1 vref_1 i/o l28p_1 h gnd i/o l16n_0 gnd i/o l25p_1 input i/o l27n_1 i/o l27p_1 gnd i/o l26n_1 i/o l26p_1 input j gnd vccint vccaux i/o l25n_1 i/o l23p_1 i/o l23n_1 a0 i/o l24p_1 i/o l24n_1 input vcco_1 i/o l22n_1 a1 k vccint gnd vccint input vcco_1 input vref_1 i/o l22p_1 a2 l vccint vccint gnd i/o gnd input vccaux i/o l17n_1 vref_1 gnd m vccint gnd vccint input i/o l16n_1 a11 i/o l16p_1 a12 i/o l15n_1 i/o l15p_1 i/o l17p_1 input n vccint gnd i/o l14n_1 i/o l14p_1 i/o l12p_1 i/o l12n_1 vref_1 gnd input vcco_1 i/o l13n_1 p input l24n_2 i/o l27p_2 input i/o l10n_1 vcco_1 i/o l09p_1 i/o l09n_1 i/o l11p_1 i/o l11n_1 i/o l13p_1 r vcco_2 input l24p_2 i/o l27n_2 input l31n_2 vref_2 i/o l10p_1 input i/o l06p_1 i/o l06n_1 input gnd i/o l08n_1 t i/o l23n_2 din d0 i/o l26p_2 i/o l26n_2 vref_2 input l31p_2 i/o l33n_2 gnd input i/o l04n_1 i/o l07n_1 vref_1 i/o l07p_1 i/o l08p_1 u i/o l23p_2 m0 gnd i/o l29p_2 vcco_2 i/o l33p_2 input vccaux i/o l04p_1 i/o l03p_1 vcco_1 i/o l05n_1 v i/o l25p_2 i/o l29n_2 i/o l32n_2 input l34p_2 i/o l36n_2 i/o l38p_2 a21 i/o l40n_2 cclk i/o l03n_1 vref_1 i/o l02n_1 a13 i/o l05p_1 w i/o l25n_2 i/o l28n_2 i/o l32p_2 input l34n_2 i/o l36p_2 i/o l38n_2 a20 i/o l40p_2 vs0 a17 gnd i/o l02p_1 a14 i/o l01n_1 a15 y i/o m1 vcco_2 i/o l28p_2 i/o l30p_2 gnd i/o l35p_2 a23 vcco_2 input l37n_2 i/o l39n_2 vs1 a18 done i/o l01p_1 a16 a a gnd i/o i/o i/o l30n_2 i/o i/o l35n_2 a22 i/o input l37p_2 i/o l39p_2 vs2 a19 i/o vref_2 gnd a b bank 1 bank 0 bank 2 gclk3 d1 l22n_2 i/o gclk2 d2 l22p_2 i/o input l21n_2 gclk1 m2 gclk0 rdwr_b l21p_2 input rhclk2 a8 l19p_1 i/o l19n_1 trdy1 rhclk3 a rhclk6 a 4 l21p_1 i/o rhclk7 a3 l21n_1 i/o i/o l20p_1 a6 k4 rhcl irdy1 7 a5 l20n_1 i/o rhclk5 rhclk1 a9 l18n_1 i/o rhclk0 a10 l18p_1 i/o ds312_11_031105 pinout descriptions 72 www.xilinx.com ds312-4 (v1.1) march 21, 2005 advance product specification r revision history the following table shows the revision history for this document. the spartan-3e family data sheet ds312-1, spartan-3e fpga family: introduction and ordering information (module 1) ds312-2, spartan-3e fpga family: functional description (module 2) ds312-3, spartan-3e fpga family: dc and switching characteristics (module 3) ds312-4, spartan-3e fpga family: pinout descriptions (module 4) date version revision 03/01/05 1.0 initial xilinx release. 03/21/05 1.1 added xc3s250e in the cp132 package to ta b l e 6 . corrected number of differential i/o pairs on cp132. added pinout and footprint information for the cp132, fg400, and fg484 packages. removed irdy and trdy pins from the vq100, tq144, and pq208 packages. |
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